G2R-14-12VDC Datasheet, PDF (68/73 Pages) Texas Instruments – Ultralow Power NTSC/PAL/SECAM Video Decoder With RObust Sync Detector

3.3.3.2 I²C Host Port Timing
PARAMETER
t1
Bus free time between STOP and START
t2
Setup time for a (repeated) START condition
t3
Hold time (repeated) START condition
t4
Setup time for a STOP condition
t5
Data setup time
t6
Data hold time
t7
Rise time VC1(SDA) and VC0(SCL) signal
t8
Fall time VC1(SDA) and VC0(SCL) signal
Cb
Capacitive load for each bus line
fI2C
I2C clock frequency
Stop Start
VC1 (SDA)
t1
VC0 (SCL)
Data
t6
t2
t7
TEST CONDITIONS
MIN TYP MAX UNIT
1.3
µs
0.6
µs
0.6
µs
0.6
ns
100
ns
0
0.9 µs
250
ns
250
ns
400 pF
400 kHz
Stop
t3
t8
t6
t4
t5
Figure 3−2. I²C Host Port Timing
3−4