G2R-14-12VDC Datasheet, PDF (23/73 Pages) Texas Instruments – Ultralow Power NTSC/PAL/SECAM Video Decoder With RObust Sync Detector

2.17 Genlock Control and RTC
A Genlock control (GLCO) function is provided to support a standard video encoder to synchronize its internal color
oscillator for properly reproduced color with unstable timebase sources like VCRs.
The frequency control word of the internal color subcarrier digital control oscillator (DTO) and the subcarrier phase
reset bit are transmitted via terminal 23 (GLCO). The frequency control word is a 23-bit binary number. The frequency
of the DTO can be calculated from the following equation:
F ^F₂ F dto ⁼
x ^ctrl
23
sclk
where F_dto is the frequency of the DTO, F_ctrl is the 23-bit DTO frequency control, and F_sclk is the frequency of the
SCLK.
2.17.1 TVP5150A Genlock Control Interface
A write of 1 to bit 4 of the chrominance control register at I²C subaddress 1Ah causes the subcarrier DTO phase reset
bit to be sent on the next scan line on GLCO. The active low reset bit occurs 7 SCLKs after the transmission of the
last bit of DCO frequency control. Upon the transmission of the reset bit, the phase of the TVP5150A internal
subcarrier DCO is reset to zero.
A Genlock slave device can be connected to the GLCO terminal and uses the information on GLCO to synchronize
its internal color phase DCO to achieve clean line and color lock.
Figure 2−6 shows the timing diagram of the GLCO mode.
SCLK
GLCO
MSB
LSB
>128 SCLK
22 21
0
23 SCLK
23-Bit Frequency Control
1 SCLK
Start Bit
Figure 2−6. GLCO Timing
7 SCLK
1 SCLK
DCO Reset Bit
2−12