G2R-14-12VDC Datasheet, PDF (11/73 Pages) Texas Instruments – Ultralow Power NTSC/PAL/SECAM Video Decoder With RObust Sync Detector

Table 1−1. Terminal Functions (Continued)
TERMINAL
NAME
I/O
NUMBER
Digital Section
DESCRIPTION
AVID
Active video indicator. This signal is high during the horizontal active time of the video output. AVID
26
O toggling during vertical blanking intervals is controlled by bit 2 of the active video cropping start pixel
LSB register at address 12h (see Section 2.20.18).
DGND
19
I Digital ground
DVDD
20
I Digital supply. Connect to 1.8-V digital supply
FID/GLCO
FID: Odd/even field indicator or vertical lock indicator. For the odd/even indicator, a 1 indicates the odd
field.
23
O GLCO: This serial output carries color PLL information. A slave device can decode the information to
allow chroma frequency control from the TVP5150A decoder. Data is transmitted at the SCLK rate in
Genlock mode. In RTC mode, SCLK/4 is used.
HSYNC
25
O Horizontal synchronization signal
INTREQ/GPCL/
VBLK
INTREQ: Interrupt request output.
GPCL: General-purpose control logic. This terminal has two functions:
27
I/O 1. General-purpose output. In this mode the state of GPCL is directly programmed via I2C.
2. Vertical blank output. In this mode the GPCL terminal is used to indicate the vertical blanking interval
of the output video. The beginning and end times of this signal are programmable via I2C.
IO_DVDD
10
I Digital supply. Connect to 3.3 V.
PDN
28
I
Power-down terminal (active low). Puts the decoder in standby mode. Preserves the value of the
registers.
RESETB
SCL
8
I
Active-low reset. RESETB can be used only when PDN = 1.
When RESETB is pulled low, it resets all the registers, restarts the internal microprocessor.
21
I/O I2C serial clock (open drain)
PCLK/SCLK
SDA
9
O System clock at either 1x or 2x the frequency of the pixel clock.
22
I/O I2C serial data (open drain)
VSYNC/PALI
VSYNC: Vertical synchronization signal
24
O PALI: PAL line indicator or horizontal lock indicator
For the PAL line indicator, a 1 indicates a noninverted line, and a 0 indicates an inverted line.
XTAL1
XTAL2
External clock reference. The user may connect XTAL1 to an oscillator or to one terminal of a crystal
5
I oscillator. The user may connect XTAL2 to the other terminal of the crystal oscillator or not connect
6
O XTAL2 at all. One single 14.31818-MHz crystal or oscillator is needed for ITU-R BT.601 sampling, for
all supported standards.
YOUT[6:0]
YOUT(7)/I2CSEL
12−18
11
I/O Output decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync.
I2CSEL: Determines address for I2C (sampled during reset). A pullup or pulldown register is needed
(>1 kΩ) to program the terminal to the desired address.
I/O
1 = Address is 0xBA
0 = Address is 0xB8
YOUT7: MSB of output decoded ITU-R BT.656 output/YCbCr 4:2:2 output.
1−5