G2R-14-12VDC Datasheet, PDF (61/73 Pages) Texas Instruments – Ultralow Power NTSC/PAL/SECAM Video Decoder With RObust Sync Detector

2.20.61 FIFO Interrupt Threshold Register
Address
C8h
Default
80h
7
6
5
4
3
2
1
0
Number of words
This register is programmed to trigger an interrupt when the number of words in the FIFO exceeds this value (default
80h). This interrupt must be enabled at address C1h. 1 word equals 2 bytes.
2.20.62 FIFO Reset Register
Address
C9h
Default
00h
7
6
5
4
3
2
1
0
Any data
Writing any data to this register resets the FIFO and clears any data present.
2.20.63 Line Number Interrupt Register
Address
CAh
Default
00h
7
6
5
4
3
2
1
0
Field 1 enable Field 2 enable
Line number
This register is programmed to trigger an interrupt when the video line number matches this value in bits 5:0. This
interrupt must be enabled at address C1h. The value of 0 or 1 does not generate an interrupt.
Field 1 enable:
0 = Disabled (default)
1 = Enabled
Field 2 enable:
0 = Disabled (default)
1 = Enabled
Line number: (default 00h)
2.20.64 Pixel Alignment Registers
Address
CBh
Default
59h
CCh
03h
Address
7
6
5
4
3
2
1
0
CBh
Switch pixel [7:0]
CCh
Reserved
Switch pixel [9:8]
These registers form a 10-bit horizontal pixel position from the falling edge of sync, where the VDP controller initiates
the program from one line standard to the next line standard; for example, the previous line of teletext to the next line
of closed caption. This value must be set so that the switch occurs after the previous transaction has cleared the delay
in the VDP, but early enough to allow the new values to be programmed before the current settings are required.
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