G2R-14-12VDC Datasheet, PDF (22/73 Pages) Texas Instruments – Ultralow Power NTSC/PAL/SECAM Video Decoder With RObust Sync Detector

2.15.2.2 Read Phase 2
Step 7
0
I2C Start (master)
S
Step 8
I2C General address (master)
7
6
5
4
3
2
1
0
1
0
1
1
1
0
X
1
Step 9
9
I2C Acknowledge (slave)
A
Step 10
I2C Read data (slave)
Step 11†
I2C Not acknowledge (master)
7
Data
9
A
6
Data
5
Data
4
Data
3
Data
2
Data
1
Data
0
Data
Step 12
0
I2C Stop (master)
P
† _{Repeat steps 10 and 11 for all bytes read. Master does not acknowledge the last read data received.}
2.15.2.3 I²C Timing Requirements
The TVP5150A decoder requires delays in the I²C accesses to accommodate its internal processor’s timing. In
accordance with I²C specifications, the TVP5150A decoder holds the I²C clock line (SCL) low to indicate the wait
period to the I²C master. If the I²C master is not designed to check for the I²C clock line held-low condition, then the
maximum delays must always be inserted where required. These delays are of variable length; maximum delays are
indicated in the following diagram:
Normal register writing address 00h−8Fh (addresses 90h−FFh do not require delays)
Slave address
Start
(B8h)
Ack
Subaddress
Ack
Data
(XXh)
Ack
Wait 64 µs Stop
2.16 Clock Circuits
An internal line-locked PLL generates the system and pixel clocks. A 14.31818-MHz clock is required to drive the PLL.
This may be input to the TVP5150A decoder on terminal 5 (XTAL1), or a crystal of 14.31818-MHz fundamental
resonant frequency may be connected across terminals 5 and 6 (XTAL2). Figure 2−5 shows the reference clock
configurations. For the example crystal circuit shown (a parallel-resonant crystal with 14.31818-MHz fundamental
frequency), the external capacitors must have the following relationship:
C_L1 = C_L2 = 2C_L − C_STRAY,
where C_STRAY is the terminal capacitance with respect to ground. Figure 2−5 shows the reference clock
configurations.
TVP5150A
5
XTAL1
6
XTAL2
14.31818-MHz
TTL Clock
TVP5150A
XTAL1
14.31818-MHz
Crystal
5
CL1
6
CL2
XTAL2
Figure 2−5. Reference Clock Configurations
2−11