AM1806_11 Datasheet, PDF (61/244 Pages) Texas Instruments – AM1806 ARM Microprocessor

AM1806
www.ti.com
SPRS658C – FEBRUARY 2010 – REVISED APRIL 2011
4.2 Recommended Operating Conditions
NAME
DESCRIPTION
CONDITION
MIN
CVDD
Core Logic Supply Voltage (variable) 1.3V operating point
1.25
1.2V operating point
1.14
1.1V operating point
1.05
1.0V operating point
0.95
RVDD
456 MHz versions
1.25
Internal RAM Supply Voltage
375 MHz versions
1.14
RTC_CVDD ⁽¹⁾ RTC Core Logic Supply Voltage
0.9
PLL0_VDDA
PLL0 Supply Voltage
1.14
PLL1_VDDA
PLL1 Supply Voltage
1.14
USB_CVDD
USB0 Core Logic Supply Voltage
1.14
USB0_VDDA18 USB0 PHY Supply Voltage
1.71
USB0_VDDA33 USB0 PHY Supply Voltage
3.15
Supply
Voltage
DVDD18 ⁽²⁾
1.8V Logic Supply
1.71
DDR_DVDD18
(2)
DDR2 PHY Supply Voltage
1.71
NOM
1.3
1.2
1.1
1.0
1.3
1.2
1.2
1.2
1.2
1.2
1.8
3.3
1.8
1.8
MAX
1.35
1.32
1.16
1.05
1.35
1.32
1.32
1.32
1.32
1.32
1.89
3.45
1.89
1.89
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
V
Supply
Ground
Voltage
Input High
Voltage
Input Low
USB
DDR_VREF
DDR2/mDDR reference voltage
0.49*
DDR_DVDD18
0.5*
DDR_DVDD1
8
0.51*
DDR_DVDD18
V
DDR_ZP
DDR2/mDDR impedance control,
connected via 50Ω resistor to Vss
Vss
V
DVDD3318_A
Power Group A Dual-voltage IO
Supply Voltage
1.8V operating point
3.3V operating point
1.71
3.15
1.8
3.3
1.89
V
3.45
V
DVDD3318_B
Power Group B Dual-voltage IO
Supply Voltage
1.8V operating point
3.3V operating point
1.71
3.15
1.8
3.3
1.89
V
3.45
V
DVDD3318_C
Power Group C Dual-voltage IO
Supply Voltage
1.8V operating point
3.3V operating point
1.71
3.15
1.8
3.3
1.89
V
3.45
V
VSS
Core Logic Digital Ground
V
PLL0_VSSA
PLL1_VSSA
OSCVSS ⁽³⁾
RTC_VSS ⁽³⁾
USB0_VSSA
USB0_VSSA33
V_IH
V_IL
USB0_VBUS
PLL0 Ground
PLL1 Ground
Oscillator Ground
RTC Oscillator Ground
USB0 PHY Ground
USB0 PHY Ground
High-level input voltage, Dual-voltage I/O, 3.3V⁽⁴⁾
High-level input voltage, Dual-voltage I/O, 1.8V ⁽⁴⁾
High-level input voltage, RTC_XI
High-level input voltage, OSCIN
Low-level input voltage, Dual-voltage I/O, 3.3V⁽⁴⁾
Low-level input voltage, Dual-voltage I/O, 1.8V ⁽⁴⁾
Low-level input voltage, RTC_XI
Low-level input voltage, OSCIN
USB external charge pump input
V
V
0
0
0
V
V
V
V
2
V
0.65*DVDD
0.8*RTC_CVDD
0.8*CVDD
0
V
V
V
0.8
V
0.35*DVDD
V
0.2*RTC_CVDD V
0.2*CVDD
V
5.25
V
(1) The RTC provides an option for isolating the RTC_CVDD from the CVDD to reduce current leakage when the RTC is powered
independently. If these power supplies are not isolated (CTRL.SPLITPOWER=0), RTC_CVDD must be equal to or greater than CVDD.
If these power supplies are isolated (CTRL.SPLITPOWER=1), RTC_CVDD may be lower than CVDD.
(2) DVDD18 must be powered even if all of the DVDD3318_x supplies are operated at 3.3V.
(3) When an external crystal is used oscillator (OSC_VSS, RTC_VSS) ground must be kept separate from other grounds and connected
directly to the crystal load capacitor ground. These pins are shorted to VSS on the device itself and should not be connected to VSS on
the circuit board. If a crystal is not used and the clock input is driven directly, then the oscillator VSS may be connected to board ground.
(4) These IO specifications apply to the dual-voltage IOs only and do not apply to the DDR2/mDDR . DDR2/mDDR IOs are 1.8V IOs and
adhere to the JESD79-2A standard.
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Device Operating Conditions
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