AM1806_11 Datasheet, PDF (113/244 Pages) Texas Instruments – AM1806 ARM Microprocessor

AM1806
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SPRS658C – FEBRUARY 2010 – REVISED APRIL 2011
5.11.3.11 DDR2/mDDR CK and ADDR_CTRL Routing
Figure 5-21 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a
balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A
should be maximized.
A1
T
A
A1
Figure 5-21. CK and ADDR_CTRL Routing and Topology
Table 5-34. CK and ADDR_CTRL Routing Specification
NO. PARAMETER
1 Center to Center CK-CKN Spacing⁽¹⁾
2 CK A to B/A to C Skew Length Mismatch⁽³⁾
MIN
TYP
MAX
UNIT
2w ⁽²⁾
25
Mils
3 CK B to C Skew Length Mismatch
4 Center to center CK to other DDR2/mDDR trace spacing⁽¹⁾
5 CK/ADDR_CTRL nominal trace length⁽⁴⁾
4w ⁽²⁾
CACLM-50
CACLM
25
Mils
CACLM+50 Mils
6 ADDR_CTRL to CK Skew Length Mismatch
100
Mils
7 ADDR_CTRL to ADDR_CTRL Skew Length Mismatch
8 Center to center ADDR_CTRL to other DDR2/mDDR trace spacing⁽¹⁾
9 Center to center ADDR_CTRL to other ADDR_CTRL trace spacing⁽¹⁾
10 ADDR_CTRL A to B/A to C Skew Length Mismatch⁽³⁾
4w ⁽²⁾
3w ⁽²⁾
100
Mils
100
Mils
11 ADDR_CTRL B to C Skew Length Mismatch
100
Mils
(1) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(2) w = PCB trace width as defined in Table 5-27.
(3) Series terminator, if used, should be located closest to device.
(4) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.
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Peripheral Information and Electrical Specifications 113
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