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AM1806_11 Datasheet, PDF (175/244 Pages) Texas Instruments – AM1806 ARM Microprocessor
AM1806
www.ti.com
SPRS658C – FEBRUARY 2010 – REVISED APRIL 2011
5.20.1 LCD Interface Display Driver (LIDD Mode)
NO.
16 tsu(LCD_D)
17 th(LCD_D)
Table 5-86. Timing Requirements for LCD LIDD Mode
PARAMETER
Setup time, LCD_D[15:0] valid before LCD_CLK (SYSCLK2) high
Hold time, LCD_D[15:0] valid after LCD_CLK (SYSCLK2) high
1.3V, 1.2V,
1.1V
MIN MAX
7
0
1.0V
MIN MAX
8
0
UNIT
ns
ns
Table 5-87. Switching Characteristics Over Recommended Operating Conditions for LCD LIDD Mode
NO.
PARAMETER
4 td(LCD_D_V)
Delay time, LCD_CLK (SYSCLK2) high to LCD_D[15:0] valid (write)
5 td(LCD_D_I)
Delay time, LCD_CLK (SYSCLK2) high to LCD_D[15:0] invalid (write)
6 td(LCD_E_A)
Delay time, LCD_CLK (SYSCLK2) high to LCD_AC_ENB_CS low
7 td(LCD_E_I)
Delay time, LCD_CLK (SYSCLK2) high to LCD_AC_ENB_CS high
8 td(LCD_A_A)
Delay time, LCD_CLK (SYSCLK2) high to LCD_VSYNC low
9 td(LCD_A_I)
Delay time, LCD_CLK (SYSCLK2) high to LCD_VSYNC high
10 td(LCD_W_A)
Delay time, LCD_CLK (SYSCLK2) high to LCD_HSYNC low
11 td(LCD_W_I)
Delay time, LCD_CLK (SYSCLK2) high to LCD_HSYNC high
12 td(LCD_STRB_A) Delay time, LCD_CLK (SYSCLK2) high to LCD_PCLK active
13 td(LCD_STRB_I) Delay time, LCD_CLK (SYSCLK2) high to LCD_PCLK inactive
14 td(LCD_D_Z)
Delay time, LCD_CLK (SYSCLK2) high to LCD_D[15:0] in 3-state
15 td(Z_LCD_D)
Delay time, LCD_CLK (SYSCLK2) high to LCD_D[15:0] (valid from 3-state)
1.3V, 1.2V,
1.1V
MIN MAX
0
7
0
7
0
7
0
7
0
7
0
7
0
7
0
7
0
7
0
7
0
7
0
7
1.0V
MIN MAX
0
9
0
9
0
9
0
9
0
9
0
9
0
9
0
9
0
9
0
9
0
9
0
9
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2
3
LCD_CLK
(SYSCLK2)
W_SU
(0 to 31)
4
W_STROBE
(1 to 63)
LCD_D[15:0]
Write Data
CS_DELAY
(0 to 3)
W_HOLD
(1 to 15)
5
R_SU
(0 to 31)
R_STROBE
(1 to 63)
R_HOLD
(1 to 15)
CS_DELAY
(0 to 3)
14
17
16
Read Status
15
Data[7:0]
LCD_PCLK
LCD_VSYNC
LCD_HSYNC
LCD_AC_ENB_CS
8
10
11
12
13
Not Used
9
RS
12
13
R/W
E0
E1
Figure 5-44. Character Display HD44780 Write
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Peripheral Information and Electrical Specifications 175
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