AM1806_11 Datasheet, PDF (111/244 Pages) Texas Instruments – AM1806 ARM Microprocessor

AM1806
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SPRS658C – FEBRUARY 2010 – REVISED APRIL 2011
5.11.3.8 Net Classes
Table 5-31 lists the clock net classes for the DDR2/mDDR interface. Table 5-32 lists the signal net
classes, and associated clock net classes, for the signals in the DDR2/mDDR interface. These net classes
are used for the termination and routing rules that follow.
CLOCK NET CLASS
CK
DQS0
DQS1
Table 5-31. Clock Net Class Definitions
PIN NAMES
DDR_CLKP / DDR_CLKN
DDR_DQS[0]
DDR_DQS[1]
SIGNAL NET CLASS
ADDR_CTRL
D0
D1
DQGATE
Table 5-32. Signal Net Class Definitions
ASSOCIATED CLOCK
NET CLASS
CK
DQS0
DQS1
CK, DQS0, DQS1
PIN NAMES
DDR_BA[2:0], DDR_A[13:0], DDR_CS, DDR_CAS, DDR_RAS, DDR_WE,
DDR_CKE
DDR_D[7:0], DDR_DQM0
DDR_D[15:8], DDR_DQM1
DDR_DQGATE0, DDR_DQGATE1
5.11.3.9 DDR2/mDDR Signal Termination
No terminations of any kind are required in order to meet signal integrity and overshoot requirements.
Serial terminators are permitted, if desired, to reduce EMI risk; however, serial terminations are the only
type permitted. Table 5-33 shows the specifications for the series terminators.
Table 5-33. DDR2/mDDR Signal Terminations^(1)(2)(3)
NO. PARAMETER
MIN
TYP
MAX
UNIT
1 CK Net Class
0
10
Ω
2 ADDR_CTRL Net Class
3 Data Byte Net Classes (DQS[0], DQS[1], D0, D1)⁽⁴⁾
0
22
Zo
Ω
0
22
Zo
Ω
4 DQGATE Net Class (DQGATE)
0
10
Zo
Ω
(1) Only series termination is permitted, parallel or SST specifically disallowed.
(2) Terminator values larger than typical only recommended to address EMI issues.
(3) Termination value should be uniform across net class.
(4) When no termination is used on data lines (0 Ω), the DDR2/mDDR devices must be programmed to operate in 60% strength mode.
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Peripheral Information and Electrical Specifications 111
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