AM1806_11 Datasheet, PDF (3/244 Pages) Texas Instruments – AM1806 ARM Microprocessor

AM1806
www.ti.com
SPRS658C – FEBRUARY 2010 – REVISED APRIL 2011
1.2 Description
The device is a Low-power applications processor based on ARM926EJ-S™.
The device enables OEMs and ODMs to quickly bring to market devices featuring robust operating
systems support, rich user interfaces, and high processing performance life through the maximum
flexibility of a fully integrated mixed processor solution.
The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and
processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and
memory system can operate continuously.
The ARM core has a coprocessor 15 (CP15), protection module, and Data and program Memory
Management Units (MMUs) with table look-aside buffers. It has separate 16K-byte instruction and
16K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core
also has a 8KB RAM (Vector Table) and 64KB ROM.
The peripheral set includes: one USB2.0 OTG interface; two inter-integrated circuit (I2C) Bus interfaces;
one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two multichannel
buffered serial ports (McBSP) with FIFO buffers; two SPI interfaces with multiple chip selects; four 64-bit
general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host port
interface (HPI) ; up to 9 banks of 16 pins of general-purpose input/output (GPIO) with programmable
interrupt/event generation modes, multiplexed with other peripherals; three UART interfaces (each with
RTS and CTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; 3 32-bit
enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary
pulse width modulator (APWM) outputs; and 2 external memory interfaces: an asynchronous and SDRAM
external memory interface (EMIFA) for slower memories or peripherals, and a higher speed DDR2/Mobile
DDR controller.
The Universal Parallel Port (uPP) provides a high-speed interface to many types of data converters,
FPGAs or other parallel devices. The UPP supports programmable data widths between 8- to 16-bits on
each of two channels. Single-data rate and double-data rate transfers are supported as well as START,
ENABLE and WAIT signals to provide control for a variety of data converters.
A Video Port Interface (VPIF) is included providing a flexible video input/output port.
The rich peripheral set provides the ability to control external peripheral devices and communicate with
external processors. For details on each of the peripherals, see the related sections later in this document
and the associated peripheral reference guides.
The device has a complete set of development tools for the ARM. These include C compilers, and
scheduling, and a Windows™ debugger interface for visibility into source code execution.
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AM1806 ARM Microprocessor
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