TMS320DM647_17 Datasheet, PDF (6/191 Pages) Texas Instruments – Digital Media Processor

TMS320DM647
TMS320DM648
SPRS372H – MAY 2007 – REVISED APRIL 2012
www.ti.com
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
This data manual revision history highlights the technical changes made to the SPRS372G device-specific
data manual to make it an SPRS372H revision. Applicable updates to the TMS320DM64x Digital Media
Processors device family , specifically relating to the TMS320DM647, TMS320DM648 devices which are
now in the production data (PD) stage of development, have been incorporated.
SEE
Section 1
Section 1.1
Table 2-4
Figure 6-5
Section 6.4.1
Table 6-44
Figure 6-21
Table 6-49
Section 7.2
DM647/DM648 Revision History
ADDITIONS, DELETIONS, MODIFICATIONS
External Memory Interfaces (EMIFs):
• Deleted the footnote reference (1) from "512M-Byte Address Space (1.8-V I/O)" subbullet
• Deleted associated footnote [devices are PD; SR1.0 was TMX]
Added separate Applications section (new format structure)
Terminal Functions, Power Pins:
• Added "or left unconnected" to the V_CCMON (L19) pin DESCRIPTION column [For the Advisory, see the
Device-Specific Silicon Errata.]
Corrected CLKDIR to VLYNQ to show 0 is VLYNQ, external
PLL1 Controller Device-Specific Information
• Added "[When SYSCLK4 is used as the EMIF input clock source, the actual clock goes through a
divider and the frequency would be SYSCLK4 divide-by-2 (see Figure 6-5, PLL Input Clock).]" to the
SYSCLK4 is used as the EMIFA AECLKOUT bullet [Cleared Doc Feedback]
Timing Requirements for Asynchronous Memory Cycles for EMIFA Module:
• Changed 3ns to 0ns for t_h(AOEH-EDV)
Updated to show times 3 and 4 are referred to rising edge AAOE/ASOE.
Changed 5.4ns to 4.2ns for t_w(VKIH) and t_w(VKIL).
Deleted duplicated Orderable Addendum table
6
Contents
Copyright © 2007–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TMS320DM647 TMS320DM648