TMS320DM647_17 Datasheet, PDF (115/191 Pages) Texas Instruments – Digital Media Processor

TMS320DM647
TMS320DM648
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Setup = 2
Strobe
Extended Strobe
8
9
SPRS372H – MAY 2007 – REVISED APRIL 2012
Strobe
Hold = 2
AECLKOUT
6
5
7
7
AARDY^(A)
ASSERTED
DEASSERTED
A. Polarity of the AARDY signal is programmable through the AP field of the EMIFA Async Wait Cycle Configuration
register (AWCC).
Figure 6-23. AARDY Timing
6.10.3.2 Programmable Synchronous Interface Timing
Table 6-46. Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module
(see Figure 6-24)
NO.
6
t_su(EDV-EKOH)
7
t_h(EKOH-EDV)
Setup time, read AEDx valid before AECLKOUT high
Hold time, read AEDx valid after AECLKOUT high
720, 800, 900, 1100
MIN
MAX
2
1.5
UNIT
ns
ns
Table 6-47. Switching Characteristics Over Recommended Operating Conditions for Programmable
Synchronous Interface Cycles for EMIFA Module⁽¹⁾ (see Figure 6-24-Figure 6-26)
720, 800, 900, 1100
NO.
PARAMETER
UNIT
MIN
MAX
1
t_d(EKOH-CEV)
2
t_d(EKOH-BEV)
3
t_d(EKOH-BEIV)
4
t_d(EKOH-EAV)
5
t_d(EKOH-EAIV)
8
t_d(EKOH-ADSV)
9
t_d(EKOH-OEV)
10
t_d(EKOH-EDV)
11
t_d(EKOH-EDIV)
12
t_d(EKOH-WEV)
Delay time, AECLKOUT high to ACEx valid
Delay time, AECLKOUT high to ABEx valid
Delay time, AECLKOUT high to ABEx invalid
Delay time, AECLKOUT high to AEAx valid
Delay time, AECLKOUT high to AEAx invalid
Delay time, AECLKOUT high to ASADS/ASRE valid
Delay time, AECLKOUT high to AAOE/ASOE valid
Delay time, AECLKOUT high to AEDx valid
Delay time, AECLKOUT high to AEDx invalid
Delay time, AECLKOUT high to AAWE/ASWE valid
1.3
4.9 ns
4.9 ns
1.3
ns
4.9 ns
1.3
ns
1.3
4.9 ns
1.3
4.9 ns
4.9 ns
1.3
ns
1.3
4.9 ns
(1) The following parameters are programmable via the EMIFA CE Configuration registers (CEnCFG):
• Read latency (R_LTNCY): 0-, 1-, 2-, or 3-cycle read latency
• Write latency (W_LTNCY): 0-, 1-, 2-, or 3-cycle write latency
• ACEx assertion length (CE_EXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has
been issued (CE_EXT = 0). For synchronous FIFO interface with glue, ACEx is active when AAOE/ASOE is active (CE_EXT = 1).
• Function of ASADS/ASRE (R_ENABLE): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE has deselect cycles
(R_ENABLE = 0). For FIFO interface, ASADS/ASRE has NO deselect cycles (R_ENABLE = 1).
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Peripheral Information and Electrical Specifications 115
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