TMS320DM647_17 Datasheet, PDF (178/191 Pages) Texas Instruments – Digital Media Processor

TMS320DM647
TMS320DM648
SPRS372H – MAY 2007 – REVISED APRIL 2012
www.ti.com
6.23 General-Purpose Input/Output (GPIO)
The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.
When configured as an output, a write to an internal register can control the state driven on the output pin.
When configured as an input, the state of the input is detectable by reading the state of an internal
register. In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different
interrupt/event generation modes. The GPIO peripheral provides generic connections to external devices.
The GPIO pins are grouped into banks of 16 pins per bank (i.e., bank 0 consists of GPIO [0:15]).
The GPIO peripheral supports the following:
• Up to 3.3-V GPIO pins
• Interrupts:
– Up to 16 unique GPIO[0:15] interrupts from Bank 0
– One GPIO bank (aggregated) interrupt signal from the GPIOs in Bank 1
– Interrupts can be triggered by rising and/or falling edge, specified for each interrupt capable GPIO
signal
• DMA events:
– Up to 10 unique GPIO DMA events from Bank 0
• Set/clear functionality: Firmware writes 1 to corresponding bit position(s) to set or to clear GPIO
signal(s). This allows multiple firmware processes to toggle GPIO output signals without critical section
protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to
anther process during GPIO programming).
• Separate Input/Output registers
• Output register in addition to set/clear so that, if preferred by firmware, some GPIO output signals can
be toggled by direct write to the output register(s).
• Output register, when read, reflects output drive status. This, in addition to the input register reflecting
pin status and open-drain I/O cell, allows wired logic be implemented.
The memory map for the GPIO registers is shown in Table 6-95.
For more detailed information on GPIOs, see the TMS320DM647/DM648 DSP General-Purpose
Input/Output (GPIO) User's Guide (literature number SPRUEK7).
6.23.1 GPIO Peripheral Register Descriptions
HEX ADDRESS RANGE
0x0204 8000
0x0204 8004
0x0204 8008
0x0204 800C
0x0204 8010
0x0204 8014
0x0204 8018
0x0204 801C
0x0204 8020
0x0204 8024
0x0204 8028
0x0204 802C
0x0204 8030
0x0204 8034
Table 6-95. GPIO Registers
ACRONYM
REGISTER NAME
PID
Peripheral Identification Register
-
Reserved
BINTEN
GPIO interrupt per-bank enable
GPIO Banks 0 and 1
-
Reserved
DIR
GPIO Banks 0 and 1 Direction Register (GPIO[0:31])
OUT_DATA
GPIO Banks 0 and 1 Output Data Register (GPIO[0:31])
SET_DATA
GPIO Banks 0 and 1 Set Data Register (GPIO[0:31])
CLR_DATA
GPIO Banks 0 and 1 Clear data for banks 0 and 1 (GPIO[0:31])
IN_DATA
GPIO Banks 0 and 1 Input Data Register (GPIO[0:31])
SET_RIS_TRIG GPIO Banks 0 and 1 Set Rising Edge Interrupt Register (GPIO[0:31])
CLR_RIS_TRIG GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register (GPIO[0:31])
SET_FAL_TRIG GPIO Banks 0 and 1 Set Falling Edge Interrupt Register (GPIO[0:31])
CLR_FAL_TRIG GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register (GPIO[0:31])
INSTAT
GPIO Banks 0 and 1 Interrupt Status Register (GPIO[0:31])
178 Peripheral Information and Electrical Specifications
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