TMS320DM647_17 Datasheet, PDF (124/191 Pages) Texas Instruments – Digital Media Processor

TMS320DM647
TMS320DM648
SPRS372H – MAY 2007 – REVISED APRIL 2012
www.ti.com
Table 6-53. Switching Characteristics Over Recommended Operating Conditions in Video Display Mode
for Video Data and Control Output Shown With Respect to VPxCLKINx and VPxCLKOUTx^{(1) (2)}
(see Figure 6-30)
NO.
PARAMETER
-720
-800
-900
-1100
MIN
MAX
1 t_c(VKO)
2 t_w(VKOH)
3 t_w(VKOL)
4 t_t(VKO)
5 t_d(VKIH-VKOH)
6 t_d(VKIL-VKOL)
7 t_d(VKIH-VKOL)
8 t_d(VKIL-VKOH)
9 t_{d(VKIH-VPOUTV)}
10 t_{d(VKIH-VPOUTIV)}
11 t_{d(VKOH-VPOUTV)}
12 t_{d(VKOH-VPOUTIV)}
Cycle time, VPxCLKOUTx
Pulse duration, VPxCLKOUTx high
Pulse duration, VPxCLKOUTx low
Transition time, VPxCLKOUTx
Delay time, VPxCLKINx high to VPxCLKOUTx high⁽³⁾
Delay time, VPxCLKINx low to VPxCLKOUTx low⁽³⁾
Delay time, VPxCLKINx high to VPxCLKOUTx low
Delay time, VPxCLKINx low to VPxCLKOUTx high
Delay time, VPxCLKINx high to VPxOUT valid⁽⁴⁾
Delay time, VPxCLKINx high to VPxOUT invalid⁽⁴⁾
Delay time, VPxCLKOUTx high to VPxOUT valid^{(1) (4)}
Delay time, VPxCLKOUTx high to VPxOUT invalid^{(1) (4)}
V - 0.7
VH - 0.7
VL - 0.7
1.7
0.7
V + 0.7
VH + 0.7
VL + 0.7
1.8
5
5
5
5
7
4.7
(1) V = the video input clock (VPxCLKINx) period in ns.
(2) VH is the high period of V (video input clock period) in ns and VL is the low period of V (video input clock period) in ns.
(3) Assuming non-inverted VPxCLKOUTx signal.
(4) VPxOUT consists of VPxCTLx and VPxD[19:0]
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VPxCLKINx
VPxCLKOUTx
[VCLK2P = 0]
5
2
1
3
6
VPxCLKOUTx
4
7
4
8
(Inverted)
[VCLK2P = 1]
11
12
VPxCTLx,V
PxD[19:0]
(Outputs)
9
15
10
16
VPxCTLx
(Input)
14
13
Figure 6-30. Video Port Display Data Output Timing and Control Input/Output Timing With Respect to
VPxCLKINx and VPxCLKOUTx
124 Peripheral Information and Electrical Specifications
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