TMS320DM647_17 Datasheet, PDF (28/191 Pages) Texas Instruments – Digital Media Processor

TMS320DM647
TMS320DM648
SPRS372H – MAY 2007 – REVISED APRIL 2012
www.ti.com
TERMINAL NAME
VP4CTL2/ ASADS/
ASRE
VP4D02/ ABE00
VP4D03/ABE01
VP4D04/AEA10
VP4D05
VP4D06/ACE2
VP4D07/ACE3
VP4D08/AEA00
VP4D09/AEA01
VP4D12/AEA02
VP4D13/AEA03
VP4D14/AEA04
VP4D15/AEA05
VP4D16/AEA06
VP4D17/AEA07
VP4D18/AEA08
VP4D19/AEA09
AEA23
AEA19
AECLKINSEL/AEA17
Table 2-4. Terminal Functions (continued)
NO TYPE⁽
1)
INTERNAL
PULLUP/
PULLDOWN
OPER DESCRIPTION
VOLT
K2 I/O/Z
IPD
3.3 V
Video Port 4 Control 2 or Programmable synchronous address
strobe or read-enable. For programmable synchronous interface,
the r_enable field in the ChipSelect x Configuration Register
selects between ASADS and ASRE:
– If r_enable = 0, then the ASADS/ASRE signal functions as the
ASADS signal.
– If r_enable = 1, then the ASADS/ASRE signal functions as the
ASRE signal.
L2 I/O/Z
IPU
3.3 V
Video Port 4 Data 2 or EMIFA byte-enable control 0. Decoded
from the low-order address bits. The number of address bits or
byte enables used depends on the width of external memory.
Byte-write enables for most types of memory.
M4 I/O/Z
IPU
3.3 V
Video Port 4 Data 3 or EMIFA byte-enable control 1. Number of
address bits or byte enables used depends on the width of
external memory. Byte-write enables for most types of memory.
M5 I/O/Z
IPU
3.3 V Video Port 4 Data 4 or EMIFA External Address 10 (word address)
(O/Z)
M6 I/O/Z
IPU
3.3 V Video Port 4 Data 5
L3 I/O/Z
IPU
3.3 V Video Port 4 Data 6 or EMIFA memory space enable 2
L4 I/O/Z
IPU
3.3 V Video Port 4 Data 7 or EMIFA memory space enable 3
L5 I/O/Z
IPD
3.3 V Video Port 4 Data 8 or EMIFA External Address 0 (word address)
(O/Z)
K3 I/O/Z
IPD
3.3 V Video Port 4 Data 9 or EMIFA External Address 1 (word address)
(O/Z)
K4 I/O/Z
IPD
3.3 V Video Port 4 Data 12 or EMIFA External Address 2 (word address)
(O/Z)
L6 I/O/Z
IPD
3.3 V Video Port 4 Data 13 or EMIFA External Address 3 (word address)
(O/Z)
K5 I/O/Z
IPD
3.3 V Video Port 4 Data 14 or EMIFA External Address 4 (word address)
(O/Z)
J3 I/O/Z
IPD
3.3 V Video Port 4 Data 15 or EMIFA External Address 5 (word address)
(O/Z)
J4 I/O/Z
IPD
3.3 V Video Port 4 Data 16 or EMIFA External Address 6 (word address)
(O/Z)
J5 I/O/Z
IPD
3.3 V Video Port 4 Data 17 or EMIFA External Address 7 (word address)
(O/Z)
J6 I/O/Z
IPD
3.3 V Video Port 4 Data 18 or EMIFA External Address 8 (word address)
(O/Z)
K6 I/O/Z
IPD
3.3 V Video Port 4 Data 19 or EMIFA External Address 9 (word address)
(O/Z)
EMIFA
H4 OZ
IPD
3.3 V EMIFA External Address 23 (word address) (O/Z)
H5 O/Z
IPU
3.3 V EMIFA External Address 19 (word address) (O/Z)
G4 I/O/Z
IPD
3.3 V
Select EMIFA external clock (I) (The EMIFA input clock AECLKIN
or SYSCLK4 is selected at reset via the pullup/pulldown resistor
on this pin. Note: AECLKIN is the default for the EMIFA input
clock.)
or EMIFA external address 17 (word address) (O/Z)
28
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