TMS320DM647_17 Datasheet, PDF (1/191 Pages) Texas Instruments – Digital Media Processor

TMS320DM647
TMS320DM648
www.ti.com
SPRS372H – MAY 2007 – REVISED APRIL 2012
TMS320DM647/TMS320DM648 Digital Media Processor
Check for Samples: TMS320DM647, TMS320DM648
1 Features
1
• High-Performance Digital Media Processor
• C64x+ L1/L2 Memory Architecture
– 720-MHz, 800-MHz, 900-MHz, 1.1-GHz
– 256K-bit (32K-byte) L1P Program RAM/Cache
C64x+™ Clock Rates
[Direct Mapped]
– 1.39 ns (-720), 1.25 ns (-800), 1.11 ns (-900),
– 256K-bit (32K-byte) L1D Data RAM/Cache
0.91 ns (-1100) Instruction Cycle Time
[2-Way Set-Associative]
– 5760, 6400, 7200, 8800 MIPS
– 2M-bit/256K-byte (DM647) or 4M-Bit/512K-
– Eight 32-Bit C64x+ Instructions/Cycle
– Fully Software-Compatible With C64x/Debug
byte) (DM648) L2 Unified Mapped
RAM/Cache [Flexible Allocation]
– Commercial Temperature Ranges (-720, -900,
and -1100 only)
– Extended Temperature Ranges (-800 only)
– Industrial Temperature Ranges (-720, -900,
and -1100 only)
• VelociTI.2™ Extensions to VelociTI™
Advanced Very-Long-Instruction-Word (VLIW)
TMS320C64x+™ DSP Core
– Eight Highly Independent Functional Units
With VelociTI.2 Extensions:
• Six ALUs (32-/40-Bit), Each Supports
Single 32-bit, Dual 16-bit, or Quad 8-bit
Arithmetic per Clock Cycle
• Two Multipliers Support Four 16 x 16-bit
Multiplies (32-bit Results) per Clock Cycle
or Eight 8 x 8-bit Multiplies (16-Bit
Results) per Clock Cycle
• Supports Little Endian Mode Only
• Five Configurable Video Ports
– Providing a Glueless I/F to Common Video
Decoder and Encoder Devices
– Supports Multiple Resolutions/Video
Standards
• VCXO Interpolated Control Port (VIC)
– Supports Audio/Video Synchronization
• External Memory Interfaces (EMIFs)
– 32-Bit DDR2 SDRAM Memory Controller With
512M-Byte Address Space (1.8-V I/O)
– Asynchronous 16-Bit Wide EMIF (EMIFA)
• Up to 128M-Byte Total Address Reach
• 64M-Byte Address Reach per CE Space
– Glueless Interface to Asynchronous
Memories (SRAM, Flash, and EEPROM)
– Load-Store Architecture With Non-Aligned
Support
– Synchronous Memories (SBSRAM and ZBT
SRAM)
– 64 32-bit General-Purpose Registers
– Supports Interface to Standard Sync Devices
– Instruction Packing Reduces Code Size
– All Instructions Conditional
– Additional C64x+™ Enhancements
• Protected Mode Operation
• Exceptions Support for Error Detection
and Program Redirection
• Hardware Support for Modulo Loop Auto-
Focus Module Operation
• C64x+ Instruction Set Features
– Byte-Addressable (8-/16-/32-/64-bit Data)
– 8-bit Overflow Protection
– Bit-Field Extract, Set, Clear
– Normalization, Saturation, Bit-Counting
– VelociTI.2 Increased Orthogonality
– C64x+ Extensions
• Compact 16-bit Instructions
• Additional Instructions to Support
Complex Multiplies
1
and Custom Logic (FPGA, CPLD, ASICs,
etc.)
• Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
• 3-Port Gigabit Ethernet Switch Subsystem
• Four 64-Bit General-Purpose Timers (Each
Configurable as Two 32-Bit Timers)
• One UART (With RTS and CTS Flow Control)
• One 4-wire Serial Port Interface (SPI) With Two
Chip-Selects
• Master/Slave Inter-Integrated Circuit (I2C
Bus™)
• Multichannel Audio Serial Port (McASP)
– Ten Serializers and SPDIF (DIT) Mode
• 16/32-Bit Host-Port Interface (HPI)
• Advanced Event Triggering (AET) Compatible
• 32-Bit 33-/66-MHz, 3.3-V Peripheral Component
Interconnect (PCI) Master/Slave Interface
Conforms to PCI Specification 2.3
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PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
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