TL16C450_09 Datasheet, PDF (6/27 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037C − MARCH 1988 − REVISED JANUARY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
VOH‡
VOL‡
IIkg
IOZ
PARAMETER
HIgh-level output voltage
Low-level output voltage
Input leakage current
High-impedance output current
TEST CONDITIONS
IOH = − 1 mA
IOL = 1.6 mA
VCC = 5.25 V,
VI = 0 to 5.25 V,
VSS = 0,
All other terminals floating
VCC = 5.25 V,
VSS = 0,
VO = 0 V to 5.25 V,
Chip selected, write mode,or chip deselected
MIN TYP†
2.4
MAX
0.4
UNIT
V
V
± 10 µA
± 20 µA
ICC
Supply current
VCC = 5.25 V,
TA = 25°C,
SIN, DSR, DCD, CTS, and RI at 2 V,
All other inputs at 0.8 V, Baud rate = 50 kbits/s,
XTAL1 at 4 MHz,
No load on outputs
CXTAL1 Clock input capacitance
CXTAL2 Clock output capacitance
Ci
Input capacitance
VCC = 0,
VSS = 0,
f = 1 MHz,
TA = 25°C,
All other terminals grounded
Co
Output capacitance
† _{All typical values are at VCC = 5 V, TA = 25°C.}
‡ _{These parameters apply for all outputs except XTAL2.}
10 mA
15
20 pF
20
30 pF
6
10 pF
10
20 pF
system timing requirements over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
tcR
Cycle time, read (tw7 + td8 + td9)
tcW
Cycle time, write (tw6 + td5 + td6)
tw5
Pulse duration, ADS low
tw6
Pulse duration, write strobe
tw7
Pulse duration, read strobe
twMR
Pulse duration, master reset
tsu1
Setup time, address valid before ADS↑
tsu2
Setup time, CS valid before ADS↑
tsu3
Setup time, data valid before WR1↓ or WR2↑
th1
Hold time, address low after ADS↑
th2
Hold time, CS valid after ADS↑
th3
Hold time, CS valid after WR1↑ or WR2↓
th4§
Hold time, address valid after WR1↑ or WR2↓
th5
Hold time, data valid after WR1↑ or WR2↓
th6
Hold time, CS valid after RD1↑ or RD2↓
th7§
Hold time, address valid after RD1↑ or RD2↓
td4§
Delay time, CS valid before WR1↓ or WR2↑
td5§
Delay time, address valid before WR1↓ or WR2↑
td6
Delay time, write cycle, WR1↑ or WR2↓ to ADS↓
td7§
Delay time, CS valid to RD1↓ or RD2↑
td8§
Delay time, address valid to RD1↓ or RD2↑
td9
Delay time, read cycle, RD1↑ or RD2↓ to ADS↓
§ _{Only applies when ADS is low.}
FIGURE
2, 3
2
3
2, 3
2, 3
2
2, 3
2, 3
2
2
2
3
3
2
2
2
3
3
3
MIN
175
175
15
80
80
1000
15
15
15
0
0
20
20
15
20
20
15
15
80
15
15
80
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
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