TL16C450_09 Datasheet, PDF (19/27 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037C − MARCH 1988 − REVISED JANUARY 2006
PRINCIPLES OF OPERATION
line control register (LCR) (continued)
Table 6. Number of Stop Bits Generated
Bit 2
0
1
1
1
1
Word Length Selected
by Bits 1 and 2
Any word length
5 bits
6 bits
7 bits
8 bits
Number of Stop
Bits Generated
1
1 1/2
2
2
2
D Bit 3: This bit is the parity enable bit. When bit 3 is set, a parity bit is generated in transmitted data between
the last data word bit and the first stop bit. In received data, if bit 3 is set, parity is checked. When bit 3 is
cleared, no parity is generated or checked.
D Bit 4: This bit is the even parity select bit. When parity is enabled (bit 3 is set) and bit 4 is set, even parity
(an even number of logic 1s is in the data and parity bits) is selected. When parity is enabled (bit 3 is set)
and bit 4 is clear, odd parity (an odd number of logic 1s) is selected.
D Bit 5: This is the stick parity bit. When bits 3, 4, and 5 are set, the parity bit is transmitted and checked as
cleared. When bits 3 and 5 are set and bit 4 is cleared, the parity bit is transmitted and checked as set.
D Bit 6: This bit is the break control bit. Bit 6 is set to force a break condition, i.e, a condition where the serial
output terminal (SOUT) is forced to the spacing (cleared) state. When bit 6 is cleared, the break condition
is disabled. The break condition has no affect on the transmitter logic, it only affects the serial output.
D Bit 7: This bit is the divisor latch access bit (DLAB). Bit 7 must be set to access the divisor latches of the
baud generator during a read or write. Bit 7 must be cleared during a read or write to access the receiver
buffer, the THR, or the IER.
line status register (LSR)^†
The LSR provides information to the CPU concerning the status of data transfers. The contents of this register
are summarized in Table 3 and are described in the following bulleted list.
D Bit 0: This bit is the data ready (DR) indicator for the receiver. Bit 0 is set whenever a complete incoming
character has been received and transferred into the RBR and is cleared by reading the RBR.
D Bit 1^‡: This bit is the overrun error (OE) indicator. When bit 1 is set, it indicates that before the character
in the RBR was read, it was overwritten by the next character transferred into the register. The OE indicator
is cleared every time the CPU reads the contents of the LSR.
D Bit 2^‡: This bit is the parity error (PE) indicator. When bit 2 is set, it indicates that the parity of the received
data character does not match the parity selected in the LCR (bit 4). The PE bit is cleared every time the
CPU reads the contents of the LSR.
D Bit 3^‡: This bit is the framing error (FE) indicator. When bit 3 is set, it indicates that the received character
does not have a valid (set) stop bit. The FE bit is cleared every time the CPU reads the contents of the LSR.
D Bit4^‡: This bit is the break interrupt (BI) indicator. When bit 4 is set, it indicates that the received data input
was held clear for longer than a full-word transmission time. A full-word transmission time is defined as the
total time of the start, data, parity, and stop bits. The BI bit is cleared every time the CPU reads the contents
of the LSR.
† _{The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment.}
‡ _{Bits 1 through 4 are the error conditions that produce a receiver line-status interrupt.}
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