TL16C450_09 Datasheet, PDF (15/27 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037C − MARCH 1988 − REVISED JANUARY 2006
PRINCIPLES OF OPERATION
Table 1. Register Selection
DLAB†
A2
A1
A0
REGISTER
0
L
L
L
Receiver buffer (read), transmitter holding register (write)
0
L
L
H
Interrupt enable
X
L
H
L
Interrupt identification (read only)
X
L
H
H
Line control
X
H
L
L
Modem control
X
H
L
H
Line status
X
H
H
L
Modem status
X
H
H
H
Scratch
1
L
L
L
Divisor latch (LSB)
1
L
L
H
Divisor latch (MSB)
† _{The divisor latch access bit (DLAB) is the most significant bit of the line control register. The DLAB signal is controlled}
by writing to this bit location (see Table 3).
REGISTER/SIGNAL
Interrupt enable register
Interrupt identification register
Line control register
Modem control register
Line status register
Modem status register
SOUT
INTRPT (receiver error flag)
INTRPT (received data available)
INTRPT (transmitter holding register empty)
INTRPT (modem status changes)
OUT2
RTS
DTR
OUT1
Scratch register
Divisor latch (LSB and MSB) register
Receiver buffer register
Transmitter holding register
Table 2. ACE Reset Functions
RESET
CONTROL
Master reset
Master reset
Master reset
Master reset
Master reset
Master reset
Read LSR/MR
Read RBR/MR
Read IIR/Write
THR/MR
Read MSR/MR
Master reset
Master reset
Master reset
Master reset
Master reset
Master reset
Master reset
Master reset
RESET STATE
All bits low (0 −3 forced and 4 −7 permanent)
Bit 0 is high, bits 1 and 2 are low, and bits 3 −7 are
permanently low
All bits low
All bits low
Bits 5 and 6 are high, all other bits are low
Bits 0 −3 are low, bits 4 −7 are input signals
High
Low
Low
Low
Low
High
High
High
High
No effect
No effect
No effect
No effect
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