TL16C450_09 Datasheet, PDF (21/27 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037C − MARCH 1988 − REVISED JANUARY 2006
PRINCIPLES OF OPERATION
modem status register (MSR)
The MSR is an 8-bit register that provides information about the current state of the control lines from the
modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provides change
information; when a control input from the modem changes state the appropriate bit is set. All four bits are
cleared when the CPU reads the MSR. The contents of this register are summarized in Table 3 and are
described in the following bulleted list.
D Bit 0: This bit is the delta clear to send (DCTS) indicator. Bit 0 indicates that the CTS input has changed
states since the last time it was read by the CPU. When this bit is set and the modem status interrupt is
enabled, a modem status interrupt is generated.
D Bit 1: This bit is the delta data set ready (DDSR) indicator. Bit 1 indicates that the DSR input has changed
states since the last time it was read by the CPU. When this bit is set and the modem status interrupt is
enabled, a modem status interrupt is generated.
D Bit 2: This bit is the trailing edge of ring indicator (TERI) detector. Bit 2 indicates that the RI input to the chip
has changed from a low to a high state. When this bit is set and the modem status interrupt is enabled, a
modem status interrupt is generated.
D Bit 3: This bit is the delta data carrier detect (DDCD) indicator. Bit 3 indicates that the DCD input to the chip
has changed state since the last time it was read by the CPU. When this bit is set and the modem status
interrupt is enabled, a modem status interrupt is generated.
D Bit 4: This bit is the complement of the clear to send (CTS) input. When bit 4 (loop) of the MCR is set, this
bit is equivalent to the MCR bit 1 (RTS).
D Bit 5: This bit is the complement of the data set ready (DSR) input. When bit 4 (loop) of the MCR is set,
this bit is equivalent to the MCR bit 0 (DTR).
D Bit 6: This bit is the complement of the ring indicator (RI) input. When bit 4 (loop) of the MCR is set, this
bit is equivalent to the MCRs bit 2 (OUT1).
D Bit 7: This bit is the complement of the data carrier detect (DCD) input. When bit 4 (loop) of the MCR is set,
this bit is equivalent to the MCRs bit 3 (OUT2).
programmable baud generator
The ACE contains a programmable baud generator that takes a clock input in the range between dc and 9 MHz
and divides it by a divisor in the range between 1 and (2¹⁶ −1). The output frequency of the baud generator is
sixteen times (16×) the baud rate. The formula for the divisor is:
divisor # = XTAL1 frequency input B (desired baud rate × 16)
Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must
be loaded during initialization of the ACE in order to ensure desired operation of the baud generator. When either
of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load.
Tables 7 and 8 illustrate the use of the baud generator with crystal frequencies of 1.8432 MHz and 3.072 MHz,
respectively. For baud rates of 38.4 kilobits per second and below, the error obtained is very small. The accuracy
of the selected baud rate is dependent on the selected crystal frequency.
Refer to Figure 10 for examples of typical clock circuits.
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