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TL16C450_09 Datasheet, PDF (3/27 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT
block diagram
2−9
D7 −D0
Data
Bus
Buffer
Internal
Data Bus
TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037C − MARCH 1988 − REVISED JANUARY 2006
Receiver
Buffer
Register
Receiver
Shift
Register
11 SIN
Line
Control
Register
Divisor
Latch (LS)
A0 31
A1 30
A2 29
CS0 14
CS1 15
CS2 16
ADS 28
MR 39
DISTR 25
DISTR 24
DOSTR 21
DOSTR 20
DDIS 26
CSOUT 27
XTAL1 18
XTAL2 19
Select
and
Control
Logic
Divisor
Latch (MS)
Line
Status
Register
Transmitter
Holding
Register
Modem
Control
Register
Modem
Status
Register
44
VCC 22
VSS
Power
Supply
Terminal numbers shown are for the FN package.
Interrupt
Enable
Register
Interrupt
I/O
Register
Baud
Generator
Interrupt
Control
Logic
Receiver
Timing and
Control
10 RCLK
17 BAUDOUT
Transmitter
Timing and
Control
Transmitter
Shift
Register
13 SOUT
Modem
Control
Logic
36 RTS
40 CTS
37 DTR
41 DSR
42 DCD
43 RI
38 OUT1
35 OUT2
33
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