TL16C450_09 Datasheet, PDF (17/27 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037C − MARCH 1988 − REVISED JANUARY 2006
PRINCIPLES OF OPERATION
interrupt enable register (IER)
The IER enables each of the four types of interrupts (refer to Table 4) and the INTRPT output signal in response
to an interrupt generation. By clearing bits 0 − 3, the IER can also disable the interrupt system. The contents
of this register are summarized in Table 3 and are described in the following bulleted list.
D Bit 0: This bit, when set, enables the received data available interrupt.
D Bit 1: This bit, when set, enables the THRE interrupt.
D Bit 2: This bit, when set, enables the receiver line status interrupt.
D Bit 3: This bit, when set, enables the modem status interrupt.
D Bits 4 − 7: These bits in the IER are not used and are always cleared.
interrupt identification register (IIR)
The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with
most microprocessors.
The ACE provides four prioritized levels of interrupts:
D Priority 1 − Receiver line status (highest priority)
D Priority 2 − Receiver data ready or receiver character time out
D Priority 3 −Transmitter holding register empty
D Priority 4 −Modem status (lowest priority)
When an interrupt is generated, the IIR indicates that an interrupt is pending and the type of interrupt in its three
least significant bits (bits 0, 1, and 2). The contents of this register are summarized in Table 3 and described
in Table 4.
D Bit 0: This bit can be used either in a hardwire prioritized or polled interrupt system. When bit 0 is cleared,
an interrupt is pending. When bit 0 is set, no interrupt is pending.
D Bits 1 and 2: These two bits identify the highest priority interrupt pending as indicated in Table 4.
D Bits 3 − 7: These bits in the IIR are not used and are always clear.
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