TL16C450_09 Datasheet, PDF (20/27 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037C − MARCH 1988 − REVISED JANUARY 2006
PRINCIPLES OF OPERATION
line status register (LSR)^† (continued)
D Bit 5: This bit is the THRE indicator. Bit 5 is set when the THR is empty, indicating that the ACE is ready
to accept a new character. If the THRE interrupt is enabled when the THRE bit is set, then an interrupt is
generated. THRE is set when the contents of the THR are transferred to the transmitted shift register. This
bit is cleared concurrent with the loading of the THR by the CPU.
D Bit 6: This bit is the transmitter empty (TEMT) indicator. Bit 6 is set when the THR and the transmitter shift
register are both empty. When either the THR or the transmitter shift register contains a data character, the
TEMT bit is cleared.
D Bit 7: This bit is always clear.
modem control register (MCR)
The MCR is an 8-bit register that controls an interface with a modem, data set, or peripheral device that is
emulating a modem. The contents of this register are summarized in Table 3 and are described in the following
bulleted list.
D Bit 0: This bit (DTR) controls the data terminal ready (DTR) output. Setting bit 0 forces the DTR output to
its active state (low). When bit 0 is clear, DTR goes high.
D Bit 1: This bit (RTS) controls the request to send (RTS) output in a manner identical to bit 0’s control over
the DTR output.
D Bit 2: This bit (OUT1) controls the output 1 (OUT1) signal, a user designated output signal, in a manner
identical to bit 0’s control over the DTR output.
D Bit 3: This bit (OUT2) controls the output 2 (OUT2) signal, a user designated output signal, in a manner
identical to bit 0’s control over the DTR output.
D Bit 4: This bit provides a local loopback feature for diagnostic testing of the ACE. When bit 4 is set, the
following occurs:
1. The SOUT is asserted high.
2. The SIN is disconnected.
3. The output of the transmitter shift register is looped back into the RSR input.
4. The four modem control inputs (CTS, DSR, DCD, and RI) are disconnected.
5. The four modem control outputs (DTR, RTS, OUT1, and OUT2) are internally connected to the four
modem control inputs.
6. The four modem control output terminals are forced to their inactive states (high).
In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verify
the transmit and receive data paths to the ACE. The receiver and transmitter interrupts are fully operational.
The modem control interrupts are also operational but the modem control interrupt sources are now the
lower four bits of the MCR instead of the four modem control inputs. All interrupts are still controlled by the
IER.
D Bits 5 through 7: These bits are clear.
† _{The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment.}
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