THS1041_15 Datasheet, PDF (6/42 Pages) Texas Instruments – 10-Bit, 40-MSPS ANALOG-TO-DIGITAL CONVERTER WITH PGA AND CLAMP

THS1041
SLAS289C − OCTOBER 2001 − REVISED OCTOBER 2004
electrical characteristics
over recommended operating conditions, AVDD = 3 V, DVDD = 3 V, fs = 40 MSPS/50% duty cycle, MODE = AVDD (internal reference),
differential input range = 1 Vpp and 2 Vpp, PGA = 1X, TA = Tmin to Tmax (unless otherwise noted) (continued)
dynamic performance (ADC and PGA)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
ENOB Effective number of bits
f = 4.8 MHz, −0.5 dBFS
f = 20 MHz, −0.5 dBFS
8.8 9.6
Bits
9.5
SFDR Spurious free dynamic range
f = 4.8 MHz, −0.5 dBFS
60.5
72
f = 20 MHz, −0.5 dBFS
dB
70
THD Total harmonic distortion
f = 4.8 MHz, −0.5 dBFS
f = 20 MHz, −0.5 dBFS
−72.5 −61.3
dB
− 71.6
SNR Signal-to-noise ratio
f = 4.8 MHz, −0.5 dBFS
55.7
60
f = 20 MHz, −0.5 dBFS
dB
57
SINAD Signal-to-noise and distortion
f = 4.8 MHz, −0.5 dBFS
55.6 59.7
f = 20 MHz, −0.5 dBFS
dB
59.6
BW
Full power bandwidth (−3 dB)
900
MHz
PGA (See Note 7)
PARAMETER
Gain range (linear scale)
Gain step size (linear scale)
Gain error (deviation from ideal, all gain settings)
Number of control bits
MIN
0.5
0.485
−3%
TYP MAX
4
0.5 0.515
3%
3
UNIT
V/V
V/V
Bits
clamp amplifier and clamp DAC (See Note 8)
PARAMETER
MIN
TYP
MAX
UNIT
Resolution
10
Bits
DAC output range
REFB
REFT
V
DAC differential nonlinearity
−1
1
LSB
DAC integral nonlinearity
−3
3
LSB
Clamping analog output voltage range
Clamping analog output voltage error
0.1
AVDD− 0.1
V
− 40
40
mV
Clamping analog output bias voltage
MODE = AVDD AVDD/2 − 0.1
AVDD/2 + 0.1 mV
NOTES: 7. Gain settings increment by the gain step size for eight binary settings of 000 to 111 to correspond to the ideal gain range.
8. The CLAMPOUT pin must see a load capacitance of at least 10 nF to ensure stability of the on-chip clamp buffer. When using the
clamp for dc restoration, the signal coupling capacitor should be at least 10 nF. When using the clamp buffer as a dc biasing reference,
CLAMPOUT should be decoupled to analog ground through at least a 10-nF capacitor.
6
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