THS1041_15 Datasheet, PDF (30/42 Pages) Texas Instruments – 10-Bit, 40-MSPS ANALOG-TO-DIGITAL CONVERTER WITH PGA AND CLAMP

THS1041
SLAS289C − OCTOBER 2001 − REVISED OCTOBER 2004
APPLICATION INFORMATION
driving the VREF pin (continued)
Note that the maximum current may be up to 30% higher. The user should ensure that VREF is driven from a
low noise, low drift source, well decoupled to analog ground and capable of driving the maximum I_REF.
driving REFT and REFB (external ADC references, MODE = AGND)
AVDD
REFT
To ADC Core
AGND
AVDD
2 kΩ
REFB
To ADC Core
AGND
Figure 46. Equivalent Circuit of REFT and REFB Inputs
designing the dc clamp
Figure 38 shows the basic operation of the clamp circuit with the analog input AIN+ coupled via an RC circuit.
AIN− must be connected to a dc source whose voltage level keeps the THS1041 differential input within the ADC
input range. The clamp voltage output level may be established by an analog voltage on the CLAMPIN pin or
by programming the on-chip clamp DAC.
(Note that it is possible to reverse the AIN+ and AIN− connections if signal inversion is also required. The
following section assumes that the signal is coupled to AIN+ and that AIN− is connected to a suitable dc bias
level).
initial clamp acquisition time
Acquisition time is the time required to reach the target clamp voltage at AIN+ when the clamp switch SW1 is
closed for the first time. The acquisition time is given by
TACQ + CIN
RlN
ǒ Ǔ ln
VC
VE
(16)
where V_C is the difference between the dc level of the input V_IN and the target clamp output voltage, V_Clamp.
V_E is the difference between the ideal V_C and the actual V_C obtained during the acquisition time. The maximum
tolerable error depends on the application requirements.
For example, consider clamping an incoming video signal that has a black level near 0.3 V to a black level of
1.3 V at the THS1041 AIN+ input. The voltage V_C required across the input coupling capacitor is thus
1.3 − 0.3 = 1 V. If a 10 mV or less clamp voltage error V_E gives acceptable system operation, the source
resistance R_IN is 20 Ω and the coupling capacitor C_IN is 1 µF, then the total clamp pulse duration required to
reach this error is:
T_ACQ = 1 µF × 20 Ω × ln(1/0.01) = 92 µs (approximate)
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