THS1041_15 Datasheet, PDF (22/42 Pages) Texas Instruments – 10-Bit, 40-MSPS ANALOG-TO-DIGITAL CONVERTER WITH PGA AND CLAMP

THS1041
SLAS289C − OCTOBER 2001 − REVISED OCTOBER 2004
PRINCIPLES OF OPERATION
onboard reference generator configuration (continued)
VBG
+
_
ADC
References
Buffer A2
MODE =
+
AVDD
2
or AVDD
VREF = External
_
REFSENSE
AVDD
Figure 33. Drive VREF Mode
AGND
operating configuration examples
Figure 34 shows a configuration using the internal ADC references for digitizing a single-ended signal with span
0 V to 2 V. Tying REFSENSE to ground gives 1 V at pin VREF. Tying MODE to AV_DD/2 then sets the REFT and
REFB voltages via the internal reference generator for a 2-V_p-p ADC input range and the CLAMPOUT pin also
provides the midscale 1-V bias for the AIN− input. Using the clamp to drive AIN− rather than connecting AIN−
directly to VREF helps to prevent kickback from the AIN− pin corrupting VREF. AIN− can be connected to VREF,
provided that VREF is well-decoupled to analog ground. Internal PGA gain setting is 1.
2V
20 Ω
AVDD/2 AVDD
1V
AIN+
0V
20 pF
MODE
20 Ω
AIN−
CLAMP
20 pF
1 µF
CLAMPOUT
10 µF
0.1 µF
CLAMPIN
VREF = 1 V
REFT
10 µF 0.1 µF
0.1 µF
REFSENSE
REFB
Figure 34. Operating Configuration: 2-V Single-Ended Input, Internal ADC References
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