THS1041_15 Datasheet, PDF (28/42 Pages) Texas Instruments – 10-Bit, 40-MSPS ANALOG-TO-DIGITAL CONVERTER WITH PGA AND CLAMP

THS1041
SLAS289C − OCTOBER 2001 − REVISED OCTOBER 2004
APPLICATION INFORMATION
driving the THS1041 analog inputs
driving the clock input
Obtaining good performance from the THS1041 requires care when driving the clock input.
Different sections of the sample-and-hold and ADC operate while the clock is low or high. The user should
ensure that the clock duty cycle remains near 50% to ensure that all internal circuits have as much time as
possible in which to operate.
The CLK pin should also be driven from a low jitter source for best dynamic performance. To maintain low jitter
at the CLK input, any clock buffers external to the THS1041 should have fast rising edges. Use a fast logic family
such as AC or ACT to drive the CLK pin, and consider powering any clock buffers separately from any other
logic on the PCB to prevent digital supply noise appearing on the buffered clock edges as jitter.
As the CLK input threshold is nominally around AV_DD/2, any clock buffers need to have an appropriate supply
voltage to drive above and below this level.
driving the sample and hold inputs
driving the AIN+ and AIN− pins
Figure 42 shows an equivalent circuit for the THS1041 AIN+ and AIN− pins. The load presented to the system
at the AIN pins comprises the switched input sampling capacitor, C_Sample, and various stray capacitances, C₁
and C₂.
AVDD
CLK
1.2 pF
AIN
C1
8 pF
C2 ^CSample
1.2 pF
AGND
CLK
+
_ _{VCM = AIN+/AIN− Common Mode Voltage}
Figure 42. Equivalent Circuit for Analog Input Pins AIN+ and AIN−
The input current pulses required to charge C_Sample and C₂ can be time averaged and the switched capacitor
circuit modelled as an equivalent resistor:
RIN2 + _CS
1
fCLK
(14)
where C_S is the sum of C_Sample and C₂. This model can be used to approximate the input loading versus source
resistance for high impedance sources.
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