THS1041_15 Datasheet, PDF (26/42 Pages) Texas Instruments – 10-Bit, 40-MSPS ANALOG-TO-DIGITAL CONVERTER WITH PGA AND CLAMP

THS1041
SLAS289C − OCTOBER 2001 − REVISED OCTOBER 2004
PRINCIPLES OF OPERATION
power management
In power-sensitive applications (such as battery-powered systems) where the THS1041 ADC is not required
to convert continuously, power can be saved between conversion intervals by placing the THS1041 into
power-down mode. This is achieved by setting bit 3 (PWDN) of the control register to 1. In power-down mode,
the device typically consumes less than 0.1 mW. Power-down mode is exited by resetting control register bit
3 to 0. On power up, typical wake-up and power-up times apply. See power supply section.
In systems where the ADC must run continuously, but where the clamp is not required, the supply current can
be reduced by approximately 1.2 mA by setting the control register bit 6 (CLDIS) to 1, which disables the clamp
circuit. Similarly, when REFSENSE is tied to AV_DD, the reference generator is disabled and supply current
reduced by approximately 1.2 mA.
output format and digital I/O
While the OE pin is held low, ADC conversion results are output at pins I/O0 (LSB) to I/O9 (MSB). The ADC input
over-range indicator is output at pin OVR. OVR is also disabled when OE is held high.
The default ADC output data format is unsigned binary (output codes 0 to 1023). The output format can be
switched to 2s complement (output codes −512 to 511) by setting control register bit 5 (TWOC) to 1.
writing to the internal registers through the digital I/O bus
Pulling pin OE high disables the I/O and OVR pin output drivers, placing the driver outputs in a high impedance
state. This allows control register data to be loaded into the THS1041 by presenting it on the I/O0 to I/O9 pins
and pulsing the WR pin high then low to latch the data into the chosen control or DAC register.
Figure 41 shows an example register write cycle where the clamp DAC code is set to 10F (hex) by writing to
clamp registers 1 and 2 (see the register map in Table 2). Pins I/O0 to I/O7 are driven to the clamp DAC code
lower byte (0F hex), and pins I/08 and I/O9 are both driven to 0 to select clamp register 1 as the data destination.
The clamp low-byte data is then loaded into this register by pulsing WR high. The top 2 bits of the DAC word
are then loaded by driving 01(hex) on pins I/O0 to I/O7 and by driving pin I/O8 to 1 and pin I/O9 to 0 to select
clamp register 2 as the data destination. WR is pulsed a second time to latch this second control word into clamp
register 2. Interface timing parameters are given in Figures 1 and 2.
OE
WR
I/O (0−9) ADC Output
Input 00F
Input 101
ADC Output
Load 0F Into
REGISTER 0
Load 01 Into
REGISTER 1
Figure 41. Example Register Write Cycle to Clamp DAC Register
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