THS1041_15 Datasheet, PDF (32/42 Pages) Texas Instruments – 10-Bit, 40-MSPS ANALOG-TO-DIGITAL CONVERTER WITH PGA AND CLAMP

THS1041
SLAS289C − OCTOBER 2001 − REVISED OCTOBER 2004
APPLICATION INFORMATION
steady-state clamp voltage error (continued)
V(Clamp)
VAIN
VCOS
VDROOP = ∆VAIN
tc
td
VM
Figure 47. Approximate Waveforms at AIN During Droop and Clamping
The voltage change at AIN during acquisition has been approximated as a linear charging ramp by assuming
that almost all of V_COS appears across R_IN, giving a charging current V_COS/R_IN (this is a reasonable
approximation when V_COS is large enough to be of concern). The voltage change at AIN during clamp
acquisition is then:
DVAIN
+
VCOS
RIN
td
CIN
(19)
The peak-to-peak voltage variation at AIN must equal the clamp droop voltage at steady state. Equating the
droop voltage to the clamp acquisition voltage change gives:
VCOS + ^RIN
IIN
tc
td
(20)
Thus for low offset voltage, keep R_IN low, design for low droop and ensure that the ratio t_d/t_c is not unreasonably
large.
reference decoupling
VREF pin
When the on-chip reference generator is enabled, the VREF pin should be decoupled to the circuit board’s
analog ground plane close to the THS1041 AGND pin via a 1-µF capacitor and a 0.1-µF ceramic capacitor.
REFT and REFB pins
In any mode of operation, the REFT and REFB pins should be decoupled as shown in Figure 48. Use short
board traces between the THS1041 and the capacitors to minimize parasitic inductance.
0.1 µF
REFT
10 µF 0.1 µF
THS1041
0.1 µF
REFB
Figure 48. Recommended Decoupling for the ADC Reference Pins REFT and REFB
32
www.ti.com