MSP430F5510_17 Datasheet, PDF (6/118 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP430F5510, MSP430F5509, MSP430F5508
MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504
MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500
SLAS645J – JULY 2009 – REVISED APRIL 2015
www.ti.com
2 Revision History
Changes from Revision I (November 2013) to Revision J
Page
• Document format and layout changes throughout, including addition of section numbering ............................... 1
• Added Device Information table .................................................................................................... 2
• Added Section 1.4 and moved all functional block diagrams to it.............................................................. 3
• Changed Figure 1-2 to show two USCIs and added note about signal access limitations ................................. 3
• Added Section 3 and moved Table 3-1 to it....................................................................................... 7
• For 48-pin options on F5510, F5509, and F5508, changed to two USCIs with note about port mapping limitations. .. 7
• Added "with port interrupt" to P2.7 description .................................................................................. 14
• Added Section 5 and moved all electrical specifications to it ................................................................. 17
• Added Section 5.2, ESD Ratings.................................................................................................. 17
• Moved Section 5.6, Thermal Characteristics ................................................................................... 21
• Changed the TYP value of C_L,eff with Test Conditions of "XTS = 0, XCAPx = 0" from 2 pF to 1 pF ..................... 26
• Added "C_VeREF+ = 20 pF" to Test Conditions for E_I.............................................................................. 40
• In Test Conditions for E_D, E_O, E_G, and E_T: changed from "(V_eREF+ – V_eREF–)min ≤ (V_eREF+ – V_eREF–)" to
"1.4 V ≤ (V_eREF+ – V_eREF–)"; changed from "C_VREF+" to "C_VeREF+" .............................................................. 40
• Added "ADC10SREFx = 11b" to Test Conditions for E_G and E_T.............................................................. 40
• Changed MIN value of AV_CC(min) with Test Conditions of "REFVSEL = {0} for 1.5 V" from 2.2 V to 1.8 V .............. 41
• Changed the value of CBREFACC in both Test Conditions for I_{AVCC_REF}; changed first row from 0 to 1; changed
second row from 1 to 0 ............................................................................................................. 42
• Changed P5.3 figure (added P5SEL.2 and XT2BYPASS inputs with AND and OR gates)............................... 83
• Changed P5SEL.3 column from X to 0 for "P5.3 (I/O)" rows.................................................................. 83
• Changed P5.5 figure (added P5SEL.5 input and OR gate) ................................................................... 85
• Changed P5SEL.5 column from X to 0 for "P5.5 (I/O)" rows.................................................................. 85
• Added ZQE and PT packages to Table 6-57 header row ..................................................................... 92
• In Table 6-58, removed second USCI and corrected first USCI device descriptor value.................................. 95
• Added Section 7 and moved Tools Support, Device Nomenclature, ESD Caution, and Trademarks sections to it ... 98
• Added Section 8 ................................................................................................................... 102
6
Revision History
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Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505
MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500