MSP430F5510_17 Datasheet, PDF (22/118 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP430F5510, MSP430F5509, MSP430F5508
MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504
MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500
SLAS645J – JULY 2009 – REVISED APRIL 2015
www.ti.com
5.7 Schmitt-Trigger Inputs – General-Purpose I/O ⁽¹⁾
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7)
(P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RST/NMI)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
V_IT+ Positive-going input threshold voltage
TEST CONDITIONS
V_CC
1.8 V
3V
MIN TYP
0.80
1.50
V_IT– Negative-going input threshold voltage
1.8 V
0.45
3V
0.75
V_hys Input voltage hysteresis (V_IT+ – V_IT–)
1.8 V
0.3
3V
0.4
R_Pull
C_I
Pullup or pulldown resistor⁽²⁾
Input capacitance
For pullup: V_IN = V_SS
For pulldown: V_IN = V_CC
V_IN = V_SS or V_CC
20
35
5
(1) Same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).
(2) Also applies to the RST pin when its pullup or pullup resistor is enabled.
MAX
1.40
2.10
1.00
1.65
0.85
1.0
UNIT
V
V
V
50 kΩ
pF
5.8 Inputs – Ports P1 and P2⁽¹⁾
(P1.0 to P1.7, P2.0 to P2.7)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
t_(int)
External interrupt timing⁽²⁾
TEST CONDITIONS
Port P1, P2: P1.x to P2.x, External trigger pulse duration
to set interrupt flag
V_CC
2.2 V, 3 V
MIN MAX UNIT
20
ns
(1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
(2) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t_(int) is met. It may be set by trigger signals
shorter than t_(int).
5.9 Leakage Current – General-Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7)
(P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RST/NMI)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
I_lkg(Px.y)
PARAMETER
High-impedance leakage current
TEST CONDITIONS
(1) (2)
V_CC
1.8 V, 3 V
MIN MAX UNIT
±50 nA
(1) The leakage current is measured with V_SS or V_CC applied to the corresponding pins, unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
5.10 Outputs – General-Purpose I/O (Full Drive Strength)
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, PJ.0
to PJ.3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
V_OH High-level output voltage
V_OL Low-level output voltage
TEST CONDITIONS
I_(OHmax) = –3 mA ⁽¹⁾
I_(OHmax) = –10 mA ⁽²⁾
I_(OHmax) = –5 mA⁽¹⁾
I_(OHmax) = –15 mA⁽²⁾
I_(OLmax) = 3 mA ⁽¹⁾
I_(OLmax) = 10 mA⁽²⁾
I_(OLmax) = 5 mA ⁽¹⁾
I_(OLmax) = 15 mA⁽²⁾
V_CC
1.8 V
3V
1.8 V
3V
MIN
V_CC – 0.25
V_CC – 0.60
V_CC – 0.25
V_CC – 0.60
V_SS
V_SS
V_SS
V_SS
MAX
V_CC
V_CC
V_CC
V_CC
V_SS + 0.25
V_SS + 0.60
V_SS + 0.25
V_SS + 0.60
UNIT
V
V
(1) The maximum total current, I_(OHmax) and I_(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
(2) The maximum total current, I_(OHmax) and I_(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
22
Specifications
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