MSP430F5510_17 Datasheet, PDF (46/118 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP430F5510, MSP430F5509, MSP430F5508
MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504
MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500
SLAS645J – JULY 2009 – REVISED APRIL 2015
www.ti.com
5.45 USB-PLL (USB Phase Locked Loop)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
MIN TYP MAX UNIT
I_PLL
f_PLL
f_UPD
t_LOCK
t_Jitter
Operating supply current
PLL frequency
PLL reference frequency
PLL lock time
PLL jitter
48
1.5
1000
7 mA
MHz
3 MHz
2 ms
ps
5.46 Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
MIN TYP MAX UNIT
DV_{CC(PGM/ERASE)}
t_READMARGIN
I_PGM
I_ERASE
I_MERASE, I_BANK
t_CPT
Program and erase supply voltage
Read access time during margin mode
Supply current from DVCC during program
Supply current from DVCC during erase
Supply current from DVCC during mass erase or bank erase
Cumulative program time
Program and erase endurance
See ⁽¹⁾
1.8
3.6 V
200 ns
3
5 mA
2 6.5 mA
2 6.5 mA
10⁴
10⁵
16 ms
cycles
t_Retention
t_Word
t_{Block, 0}
Data retention duration
Word or byte program time
Block program time for first byte or word
T_J = 25°C
100
See ⁽²⁾
64
See ⁽²⁾
49
t_{Block, 1–(N–1)}
Block program time for each additional byte or word, except for last
byte or word
See ⁽²⁾
37
t_{Block, N}
Block program time for last byte or word
See ⁽²⁾
55
t_Erase
Erase time for segment, mass erase, and bank erase when
available.
See ⁽²⁾
23
years
85 µs
65 µs
49 µs
73 µs
32 ms
(1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word write, individual byte write, and block write modes.
(2) These values are hardwired into the flash controller's state machine.
5.47 JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
f_SBW
t_SBW,Low
t_{SBW, En}
t_SBW,Rst
f_TCK
PARAMETER
Spy-Bi-Wire input frequency
Spy-Bi-Wire low clock pulse duration
Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)⁽¹⁾
Spy-Bi-Wire return to normal operation time
TCK input frequency for 4-wire JTAG⁽²⁾
V_CC
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V
3V
MIN
0
0.025
15
0
0
TYP
R_internal
Internal pulldown resistance on TEST
2.2 V, 3 V
45
60
MAX
20
15
1
100
5
10
80
UNIT
MHz
µs
µs
µs
MHz
MHz
kΩ
(1) Tools that access the Spy-Bi-Wire interface need to wait for the t_SBW,En time after pulling the TEST/SBWTCK pin high before applying
the first SBWTCK clock edge.
(2) f_TCK may be restricted to meet the timing requirements of the module selected.
46
Specifications
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MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500