LP3913 Datasheet, PDF (6/70 Pages) Texas Instruments – Power Management IC for Flash Memory-Based Portable Media Players

LP3913
SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013
www.ti.com
GENERAL ELECTRICAL CHARACTERISTICS
Unless otherwise noted, VDD = 5V, VBATT = 3.6V. Typical values and limits appearing in normal type apply for T_J = 25°C.
Limits appearing in boldface type apply over the entire junction temperature range for operation, T_J = 0°C to +125°C.
(1) (2) (3) (4)
I_{Q_BATT}
Symbol
V_POR
T_SD
T_SDH
T_TH-ALERT
VDDIO
F_CLK
Parameter
Conditions
Min
Typ
Max
Units
Battery Standby Supply
Current
All circuits off except for
POR and battery monitor.
No adapter or USB power
connected.
6
20
µA
Power-On Reset Threshold VDD Falling Edge
1.9
V
Thermal Shutdown
Threshold
160
°C
Themal Shutdown
Hysteresis
20
°C
Thermal Interrupt
Threshold
115
°C
IO Supply
Internal System Clock
Frequency
2.5
V_DD
V
2
MHz
(1) All voltages are with respect to the potential at the GND pin.
(2) Min and Max limits are specified by design, test, or statistical analysis. Typical numbers represent the most likely norm.
(3) Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
(4) Specified by design. Not production tested
I²C INTERFACE ELECTRICAL CHARACTERISTICS
Unless otherwise noted, VDDIO = 3.6V. Typical values and limits appearing in normal type apply for T_J = 25°C. Limits
appearing in boldface type apply over the entire junction temperature range for operation, T_J = 0°C to +125°C.^(1)(2)(3)(4)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V_IL
Low Level Input Voltage
I²C_SDA & I²C_SCL
0.3VDDI
O
V
V_IH
High Level Input Voltage
I²C_SDA & I²C_SCL
0.7VDDI
O
V
V_OL
Low Level Output Voltage
I²C_SDA & I²C_SCL
0
0.2VDDI
O
V
V_HYS
Schmitt Trigger Input Hysterisis I²C_SDA & I²C_SCL
0.1VDDI
O
V
F_CLK
t_BF
t_HOLD
t_CLK-LP
t_CLK-HP
t_SU
t_DATA-HOLD
t_DATA-SU
t_SU
t_TRANS
Clock Frequency
Bus-Free Time between START ⁽⁴⁾
and STOP
Hold Time Repeated START
(4)
Condition
CLK Low Period
(4)
CLK High Period
(4)
Set-up Time Repeated START ⁽⁴⁾
Condition
Data Hold Time
(4)
Data Set-up Time
(4)
Set-Up Time for STOP Condition ⁽⁴⁾
Maximum Pulse Width of Spikes ⁽⁴⁾
That Must Be Suppressed by the
Input Filter of Both Data and
CLK Signals.
400
kHz
1.3
µs
0.6
µs
1.3
µs
0.6
µs
0.6
µs
0
µs
100
ns
0.6
µs
50
µs
(1) All voltages are with respect to the potential at the GND pin.
(2) Min and Max limits are specified by design, test, or statistical analysis. Typical numbers represent the most likely norm.
(3) Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
(4) Specified by design. Not production tested.
6
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