LP3913 Datasheet, PDF (35/70 Pages) Texas Instruments – Power Management IC for Flash Memory-Based Portable Media Players

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LP3913
SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013
Figure 62. I²C Write Cycle
ack from slave
ack from slave
ack from slave
start msb Chip Address lsb w ack msb Register Add lsb ack msb DATA lsb ack stop
SCL
SDA
1 2 3 4 5 6 7 8 9 1 2 3 ...
start
id = K¶60
w ack
addr = K¶00
ack
w = write (I²C_SDA = “0”)
r = read (I²C_SDA = “1”)
ack = acknowledge (I²C_SDA pulled down by either master or slave)
rs = repeated start
id = LP3913 chip address : 60’h
DGGUHVVK¶$$GDWD ack stop
Register Read Cycle
When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in
the Read Cycle waveform.
ack from slave
Figure 63. I²C Read Cycle
ack from slave repeated start
ack from slave data from slave ack from master
start msb Chip Address lsb w ack msb Register Add lsb ack rs msb Chip Address lsb r ack msb DATA lsb ack stop
SCL
SDA
start
id = K¶60
w ack register addr = K¶10 ack rs
id = K¶60
r ack
GDWDDGGUK¶6A
ack stop
Multi-byte I²C Command Sequence
The LP3913’s I²C serial interface shall support Random register Multi-byte command sequencing: During a multi-
byte write the Master sends the Start command followed by the Device address, which is sent only once,
followed by the 8-bit register address, then 8 bits of data, The I²C slave must then accept the next random
register address followed by 8 bits of data and continue this process until the master sends a valid stop
condition.
A Typical Multi-byte random register transfer is outlined below:
Device Address, Register A Address, Ack, Register A Data, Ack Register M Address, Ack, Register M Data,
Ack Register X Address, Ack, Register X Data, Ack Register Z Address, Ack, Register Z Data, Ack, Stop
NOTE
The PMIC is not required to see the I²C device address for each transaction. A, M, X, and
Z are random numbers
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