LP3913 Datasheet, PDF (33/70 Pages) Texas Instruments – Power Management IC for Flash Memory-Based Portable Media Players

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LP3913
SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013
Figure 58. Power Down Caused by Expiring PowerACK Deadline
Power Down Caused by Expiring PowerACK deadline
CHG_DET/USBPWR
or
ONOFF
External Events
ONSTAT
(To Microprocessor)
VLDO1, VLDO2
(If LDO2ENB is logic 1 during NRST Low,
otherwise LDO2 are pin or register enabled)
VBUCK1
VBUCK2
VBUCK3
NRST
PowerACK
(From Microprocessor)
(Bit D4 in PON register and
POWERACK pin)
x
PowerACK deadline (expired)
Transition from Charger Standby Mode to Either Active or Standby Mode
While in Charger Standby mode, the battery is charged using the default values of I_PROG, EOC, V_TERM, Batt Temp
Range and USB I_SEL. In Charger Standby mode, all the regulators and the I²C are disabled. A new power-on
event is required to transition back to Active Mode. Removing the charger during Charger Standby Mode causes
a transition back to Standby Mode.
I²C-Compatible Serial Interface
I²C Signals
The LP3913 features an I²C compatible serial interface, using two dedicated pins: I²C_SCL and I²C_SDA for I²C
clock and data respectively. Both signals need a pull-up resistor according to the I²C specification. The LP3913
interface is an I²C slave that is clocked by the incoming SCL clock.
Signal timing specifications are according to the I²C bus specification. The maximum bit rate is 400 kbit/s. See
I²C specification from Philips for further details.
I²C Data Validity
The data on I²C_SDA line must be stable during the HIGH period of the clock signal (I²C_SCL), e.g., the state of
the data line can only be changed when CLK is LOW.
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