LP3913 Datasheet, PDF (49/70 Pages) Texas Instruments – Power Management IC for Flash Memory-Based Portable Media Players

LP3913
www.ti.com
SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013
LDO1 Control Register
LDO1 can be configured through its own I²C control register. The output voltage is programmable in steps of 100
mV from 1.2V to 3.3V. LDO1 gets enabled during the power-on sequence. Disable/enable control is provided
through bit D5 in the LDO1 control register after selecting the appropriate D4–0 settings, which determine the
output voltage.
The output voltage can be altered while LDO1 is enabled. When LDO1 is disabled it shunts the output to AGND
with a R_SHUNT = 200Ω (Max.).
LDO1 Control Register (08)h
Access
Data
Reset
D7–6
Read Only 0
Reserved
D5
R/W
Operation
0: disable
1: enable
D4–0
n/a
1
LDO1 Output Voltage (V)
5’h00
1.2
5’h01
1.3
5’h02
1.4
5’h03
1.5
5’h04
1.6
5’h05
1.7
5’h06
1.8
5’h07
1.9
5’h08
2.0
5’h09
2.1
5’h0A
2.2
5’h0B
2.3
5’h0C
2.4
5’h0D
2.5
5’h0E
2.6
5’h0F
2.7
5’h10
2.8
5’h11
2.9
5’h12
3.0
5’h13
3.1
5’h14
3.2
5’h15 –5’h1F
3.3
5’h08
LDO2 Control Register
LDO2 can be configured through its own I²C control register. The output voltage is programmable in steps of
100mV from 1.3V to 3.3V. LDO2 is by default disabled and can be enabled by setting bit D5 in the control
register after selecting the appropriate D4–0 settings, which determine the output voltage. LDO2 can also be
enabled through the external LDO2EN pin, which is the default enable control. With a logic 0 programmed to bit
D5 in the corresponding control register, enable/disable control is passed onto the LDO2EN pin; a logic 1 applied
to this pin enables LDO2 while a logic 0 disables the LDO2. Setting D5 to 1 in the LDO2 control register enables
LDO2, regardless of the state of the LDO2EN pin. If the system designer permanently connects the LDO2EN pin
to GND, then D5 is simply a enable/disable control bit. If the system design permanently connects the enable pin
to V_DD, then the LDO is enabled during the power-on sequence and will always be on, regardless of the state of
bit D5 in the LDO2 control register. In that particular case, the LDO2 is sequenced with the same timing as LDO1
(see Power On/Off Sequencing).
The output voltage can be altered while LDO2 is enabled. When LDO2 is disabled it shunts the output to A_GND
with a R_SHUNT = 200Ω (Max.).
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