DS90CR285MTDX Datasheet, PDF (6/25 Pages) Texas Instruments – DS90CR285/DS90CR286 +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHz

DS90CR285, DS90CR286
SNLS130C – MARCH 1999 – REVISED MARCH 2013
Receiver Switching Characteristics (continued)
Over recommended operating supply and −40°C to +85°C ranges unless otherwise specified
Symbol
RSPos0
Parameter
Receiver Input Strobe Position for Bit 0 ⁽²⁾(Figure 21)
Min
f = 66 MHz
0.7
RSPos1
Receiver Input Strobe Position for Bit 1
2.9
RSPos2
Receiver Input Strobe Position for Bit 2
5.1
RSPos3
Receiver Input Strobe Position for Bit 3
7.3
RSPos4
Receiver Input Strobe Position for Bit 4
9.5
RSPos5
Receiver Input Strobe Position for Bit 5
11.7
RSPos6
RSKM
Receiver Input Strobe Position for Bit 6
RxIN Skew Margin ⁽³⁾(Figure 22)
13.9
f = 40 MHz
490
f = 66 MHz
400
RCOP
RxCLK OUT Period (Figure 11)
15
RCOH
RxCLK OUT High Time (Figure 11)
f = 40 MHz
6.0
f = 66 MHz
4.0
RCOL
RxCLK OUT Low Time (Figure 11)
f = 40 MHz
10.0
f = 66 MHz
6.0
RSRC
RxOUT Setup to RxCLK OUT (Figure 11)
f = 40 MHz
6.5
f = 66 MHz
2.5
RHRC
RxOUT Hold to RxCLK OUT (Figure 11)
f = 40 MHz
6.0
f = 66 MHz
2.5
RCCD
RxCLK IN to RxCLK OUT Delay (Figure 13)
f = 40 MHz
4.0
f = 66 MHz
5.0
RPLLS
Receiver Phase Lock Loop Set (Figure 15)
RPDD
Receiver Powerdown Delay (Figure 19)
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Typ Max Units
1.1
1.4
ns
3.3
3.6
ns
5.5
5.8
ns
7.7
8.0
ns
9.9 10.2 ns
12.1 12.4 ns
14.3 14.6 ns
ps
ps
T
50
ns
10.0
ns
6.1
ns
13.0
ns
7.8
ns
14.0
ns
8.0
ns
8.0
ns
4.0
ns
6.7
8.0
ns
6.6
9.0
ns
10 ms
1
μs
(2) The min. and max. limits are based on the worst bit by applying a −400ps/+300ps shift from ideal position.
(3) Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter
pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window). This margin allows LVDS
interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter less than 250 ps).
AC TIMING DIAGRAMS
Figure 5. “Worst Case” Test Pattern
6
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