DS90CR285MTDX Datasheet, PDF (13/25 Pages) Texas Instruments – DS90CR285/DS90CR286 +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHz

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DS90CR285, DS90CR286
SNLS130C – MARCH 1999 – REVISED MARCH 2013
C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and
max
Tppos—Transmitter output pulse position (min and max)
RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) + ISI (Inter-symbol interference)
Cable Skew—typically 10 ps–40 ps per foot, media dependent
(1) Cycle-to-cycle jitter is less than 250 ps
(2) ISI is dependent on interconnect length; may be zero
Figure 22. Receiver LVDS Input Skew Margin
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