DS90CR285MTDX Datasheet, PDF (5/25 Pages) Texas Instruments – DS90CR285/DS90CR286 +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHz

DS90CR285, DS90CR286
www.ti.com
SNLS130C – MARCH 1999 – REVISED MARCH 2013
Transmitter Switching Characteristics
Over recommended operating supply and −40°C to +85°C ranges unless otherwise specified
Symbol
Parameter
Min
Typ
LLHT
LVDS Low-to-High Transition Time (Figure 6)
0.5
LHLT
LVDS High-to-Low Transition Time (Figure 6)
0.5
TCIT
TxCLK IN Transition Time (Figure 8)
TCCS
TxOUT Channel-to-Channel Skew (Figure 9)
250
TPPos0
Transmitter Output Pulse Position for Bit0
f = 40 MHz
−0.4
0
(1)_{(Figure 20)}
TPPos1
Transmitter Output Pulse Position for Bit1
3.1
3.3
TPPos2
Transmitter Output Pulse Position for Bit2
6.5
6.8
TPPos3
Transmitter Output Pulse Position for Bit3
10.2
10.4
TPPos4
Transmitter Output Pulse Position for Bit4
13.7
13.9
TPPos5
Transmitter Output Pulse Position for Bit5
17.3
17.6
TPPos6
Transmitter Output Pulse Position for Bit6
21.0
21.2
TPPos0
Transmitter Output Pulse Position for Bit0
f = 66 MHz
−0.4
0
(2)_{(Figure 20)}
TPPos1
Transmitter Output Pulse Position for Bit1
1.8
2.2
TPPos2
Transmitter Output Pulse Position for Bit2
4.0
4.4
TPPos3
Transmitter Output Pulse Position for Bit3
6.2
6.6
TPPos4
Transmitter Output Pulse Position for Bit4
8.4
8.8
TPPos5
Transmitter Output Pulse Position for Bit5
10.6
11.0
TPPos6
Transmitter Output Pulse Position for Bit6
12.8
13.2
TCIP
TxCLK IN Period (Figure 10 )
15
T
TCIH
TxCLK IN High Time (Figure 10)
0.35T
0.5T
TCIL
TxCLK IN Low Time (Figure 10)
0.35T
0.5T
TSTC
TxIN Setup to TxCLK IN (Figure 10)
2.5
THTC
TxIN Hold to TxCLK IN (Figure 10)
0
TCCD
TxCLK IN to TxCLK OUT Delay @ 25°C,V_CC=3.3V (Figure 12)
3
3.7
TPLLS
Transmitter Phase Lock Loop Set (Figure 14)
TPDD
Transmitter Powerdown Delay (Figure 18)
Max
1.5
1.5
5
0.4
4.0
7.6
11.0
14.6
18.2
21.8
0.3
2.5
4.7
6.9
9.1
11.3
13.5
50
0.65T
0.65T
5.5
10
100
(1) The min. and max. are based on the actual bit position of each of the 7 bits within the LVDS data stream across PVT.
(2) The min. and max. limits are based on the worst bit by applying a −400ps/+300ps shift from ideal position.
Units
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
Receiver Switching Characteristics
Over recommended operating supply and −40°C to +85°C ranges unless otherwise specified
Symbol
Parameter
Min
CLHT
CMOS/TTL Low-to-High Transition Time (Figure 7)
CHLT
RSPos0
CMOS/TTL High-to-Low Transition Time (Figure 7)
Receiver Input Strobe Position for Bit 0 ⁽¹⁾(Figure 21)
f = 40 MHz
1.0
RSPos1
Receiver Input Strobe Position for Bit 1
4.5
RSPos2
Receiver Input Strobe Position for Bit 2
8.1
RSPos3
Receiver Input Strobe Position for Bit 3
11.6
RSPos4
Receiver Input Strobe Position for Bit 4
15.1
RSPos5
Receiver Input Strobe Position for Bit 5
18.8
RSPos6
Receiver Input Strobe Position for Bit 6
22.5
Typ Max Units
2.2
5.0
ns
2.2
5.0
ns
1.4 2.15 ns
5.0
5.8
ns
8.5 9.15 ns
11.9 12.6 ns
15.6 16.3 ns
19.2 19.9 ns
22.9 23.6 ns
(1) The min. and max. are based on the actual bit position of each of the 7 bits within the LVDS data stream across PVT.
Copyright © 1999–2013, Texas Instruments Incorporated
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