DS90CR285MTDX Datasheet, PDF (14/25 Pages) Texas Instruments – DS90CR285/DS90CR286 +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHz

DS90CR285, DS90CR286
SNLS130C – MARCH 1999 – REVISED MARCH 2013
www.ti.com
DS90CR285 DGG (TSSOP) Package Pin Description — Channel Link Transmitter
Pin Name
I/O No.
Description
TxIN
I 28 TTL level input.
TxOUT+
O 4 Positive LVDS differential data output.
TxOUT−
O 4 Negative LVDS differential data output.
TxCLK IN
I 1 TTL IeveI clock input. The rising edge acts as data strobe. Pin name TxCLK IN.
TxCLK OUT+
O 1 Positive LVDS differential clock output.
TxCLK OUT−
O 1 Negative LVDS differential clock output.
PWR DWN
I 1 TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power down.
V_CC
GND
I 4 Power supply pins for TTL inputs.
I 5 Ground pins for TTL inputs.
PLL V_CC
PLL GND
I 1 Power supply pin for PLL.
I 2 Ground pins for PLL.
LVDS V_CC
LVDS GND
I 1 Power supply pin for LVDS outputs.
I 3 Ground pins for LVDS outputs.
Pin Name
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DWN
V_CC
GND
PLL V_CC
PLL GND
LVDS V_CC
LVDS GND
DS90CR286 DGG (TSSOP) Package Pin Description — Channel Link Receiver
I/O No.
Description
I 4 Positive LVDS differential data inputs.
I 4 Negative LVDS differential data inputs.
O 28 TTL level data outputs.
I 1 Positive LVDS differential clock input.
I 1 Negative LVDS differential clock input.
O 1 TTL level clock output. The rising edge acts as data strobe. Pin name RxCLK OUT.
I 1 TTL level input.When asserted (low input) the receiver outputs are low.
I 4 Power supply pins for TTL outputs.
I 5 Ground pins for TTL outputs.
I 1 Power supply for PLL.
I 2 Ground pin for PLL.
I 1 Power supply pin for LVDS inputs.
I 3 Ground pins for LVDS inputs.
14
Submit Documentation Feedback
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: DS90CR285 DS90CR286