DS90CR285MTDX Datasheet, PDF (16/25 Pages) Texas Instruments – DS90CR285/DS90CR286 +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHz

DS90CR285, DS90CR286
SNLS130C – MARCH 1999 – REVISED MARCH 2013
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impedance of the selected physical media (this impedance should also match the value of the termination
resistor that is connected across the differential pair at the receiver's input). Finally, the location of the CHANNEL
LINK TxOUT/RxIN pins should be as close as possible to the board edge so as to eliminate excessive pcb runs.
All of these considerations will limit reflections and crosstalk which adversely effect high frequency performance
and EMI.
UNUSED INPUTS
All unused inputs at the TxIN inputs of the transmitter must be tied to ground. All unused outputs at the RxOUT
outputs of the receiver must then be left floating.
INPUTS
The TxIN and control inputs are compatible with LVCMOS and LVTTL levels. These pins are not 5V tolerant.
TERMINATION
Use of current mode drivers requires a terminating resistor across the receiver inputs. The CHANNEL LINK
chipset will normally require a single 100Ω resistor between the true and complement lines on each differential
pair of the receiver input. The actual value of the termination resistor should be selected to match the differential
mode characteristic impedance (90Ω to 120Ω typical) of the cable. Figure 23 shows an example. No additional
pull-up or pull-down resistors are necessary as with some other differential technologies such as PECL. Surface
mount resistors are recommended to avoid the additional inductance that accompanies leaded resistors. These
resistors should be placed as close as possible to the receiver input pins to reduce stubs and effectively
terminate the differential lines.
DECOUPLING CAPACITORS
Bypassing capacitors are needed to reduce the impact of switching noise which could limit performance. For a
conservative approach three parallel-connected decoupling capacitors (Multi-Layered Ceramic type in surface
mount form factor) between each V_CC and the ground plane(s) are recommended. The three capacitor values are
0.1 μF, 0.01μF and 0.001 μF. An example is shown in Figure 24. The designer should employ wide traces for
power and ground and ensure each capacitor has its own via to the ground plane. If board space is limiting the
number of bypass capacitors, the PLL V_CC should receive the most filtering/bypassing. Next would be the LVDS
V_CC pins and finally the logic V_CC pins.
Figure 23. LVDS Serialized Link Termination
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