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DAC8550_16 Datasheet, PDF (6/31 Pages) Texas Instruments – 16-bit, Ultra-Low Glitch, Voltage Output Digital-To-Analog Converter
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DAC8550
SLAS476F – MARCH 2006 – REVISED MARCH 2016
Electrical Characteristics (continued)
VDD = 2.7 V to 5.5 V, –40°C to 105°C range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
POWER REQUIREMENTS
IDD
Supply current
POWER EFFICIENCY
Normal mode, input code equals mid-
scale, no load, does not include reference
current, VIH = VDD, VIL = GND
All power-down modes,
VIH = VDD, VIL = GND
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
IOUT/IDD
ILOAD = 2 mA, VDD = 5 V
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MIN TYP
160
140
0.2
0.05
89%
MAX UNIT
250
240
μA
2
2
6.6 Timing Characteristics
VDD = 2.7 V to 5.5 V, all specifications –40°C to 105°C (unless otherwise noted)(1)(2)
PARAMETER
TEST CONDITIONS
t1 (3)
SCLK cycle time
t2
SCLK HIGH time
t3
SCLK LOW time
t4
SYNC to SCLK rising edge setup time
t5
Data setup time
t6
Data hold time
t7
24th SCLK falling edge to SYNC rising edge
t8
Minimum SYNC HIGH time
t9
24th SCLK falling edge to SYNC falling edge
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 5.5 V
MIN
TYP
MAX
50
33
13
13
22.5
13
0
0
5
5
4.5
4.5
0
0
50
33
100
(1) All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH) / 2.
(2) See Figure 1.
(3) Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V and 20 MHz at VDD = 2.7 V to 3.6 V.
SCLK
SYNC
1
t8
t4
t1
t9
24
t3
t2
t7
t6
t5
DIN
DB23
DB0
DB23
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 1. Serial Write Operation
6
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