DAC8550_16 Datasheet, PDF (23/31 Pages) Texas Instruments – 16-bit, Ultra-Low Glitch, Voltage Output Digital-To-Analog Converter

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DAC8550
SLAS476F – MARCH 2006 – REVISED MARCH 2016
System Examples (continued)
The 68HC11 should be configured so that its CPOL bit is '0' and its CPHA bit is '1'. This configuration causes
data appearing on the MOSI output to be valid on the falling edge of SCK. When data are being transmitted to
the DAC, the SYNC line is held LOW (PC7). Serial data from the 68HC11 are transmitted in 8-bit bytes with only
eight falling clock edges occurring in the transmit cycle. (Data are transmitted MSB first.) In order to load data to
the DAC8550, PC7 is left LOW after the first eight bits are transferred, then a second and third serial write
operation are performed to the DAC. PC7 is taken HIGH at the end of this procedure.
9 Power Supply Recommendations
The DAC8550 can operate within the specified supply voltage range of 2.7 V to 5.5 V. The power applied to V_DD
should be well-regulated and low-noise. Switching power supplies and dc/dc converters often have high-
frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-
frequency spikes. This noise can easily couple into the DAC output voltage through various paths between the
power connections and analog output. In order to further minimize noise from the power supply, a strong
recommendation is to include a 1-μF to 10-μF capacitor and 0.1-μF bypass capacitor. The current consumption
on the V_DD pin, the short-circuit current limit, and the load current for the device is listed in the Electrical
Characteristics. The power supply must meet the aforementioned current requirements.
10 Layout
10.1 Layout Guidelines
A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power
supplies.
The DAC8550 offers single-supply operation and is used often in close proximity with digital logic,
microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and
the higher the switching speed, the more difficult it is to keep digital noise from appearing at the output.
Due to the single ground pin of the DAC8550, all return currents, including digital and analog return currents for
the DAC, must flow through a single point. Ideally, GND would be connected directly to an analog ground plane.
This plane would be separate from the ground connection for the digital components until they were connected at
the power-entry point of the system.
As with the GND connection, V_DD should be connected to a 5-V power-supply plane or trace that is separate
from the connection for digital logic until they are connected at the power-entry point. In addition, a 1-μF to 10-μF
capacitor and 0.1-μF bypass capacitor are strongly recommended. In some situations, additional bypassing may
be required, such as a 100-μF electrolytic capacitor or even a Pi filter made up of inductors and capacitors, all
designed to essentially low-pass filter the 5-V supply, removing the high-frequency noise.
10.2 Layout Example
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4
5
Figure 59. Layout Diagram
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