DAC8550_16 Datasheet, PDF (5/31 Pages) Texas Instruments – 16-bit, Ultra-Low Glitch, Voltage Output Digital-To-Analog Converter

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DAC8550
SLAS476F – MARCH 2006 – REVISED MARCH 2016
6.5 Electrical Characteristics
V_DD = 2.7 V to 5.5 V, –40°C to 105°C range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
STATIC PERFORMANCE⁽¹⁾
Resolution
E_L
Relative accuracy
Measured by line passing through codes ^DAC8550
–32283 and 32063
DAC8550B
E_D
Differential nonlinearity
E_O
Zero-code error
E_FS
Full-scale error
E_G
Gain error
Zero-code error drift
16-bit monotonic
Measured by line passing through codes –32283 and 32063
Measured by line passing through codes –32283 and 32063
Measured by line passing through codes –32283 and 32063
Gain temperature coefficient
PSRR
Power-supply rejection ratio
OUTPUT CHARACTERISTICS⁽²⁾
V_O
Output voltage range
t_SD
Output voltage settling time
SR
Slew rate
Capacitive load stability
Code change glitch impulse
Digital feedthrough
z_O
DC output impedance
I_OS
Short-circuit current
t_ON
Power-up time
AC PERFORMANCE
SNR
Signal-to-noise ratio
THD
Total harmonic distortion
SFDR
Spurious-free dynamic range
SINAD
Signal-to-noise and distortion
REFERENCE INPUT
V_REF
Reference voltage
I_I(REF)
Reference current input range
z_I(REF)
Reference input impedance
LOGIC INPUTS ⁽²⁾
Input current
V_IL
Low-level input voltage
V_IH
High-level input voltage
Pin capacitance
R_L = 2 kΩ, C_L = 200 pF
To ±0.003% FSR, 1200h to 8D00h, R_L = 2 kΩ, 0 pF < C_L < 200 pF
R_L = 2 kΩ, C_L = 500 pF
R_L = ∞
R_L = 2 kΩ
1 LSB change around major carry
SCLK toggling, FSYNC high
At mid-code input
V_DD = 5 V
V_DD = 3 V
Coming out of power-down mode, V_DD = 5 V
Coming out of power-down mode, V_DD = 3 V
BW = 20 kHz, V_DD = 5 V, f_OUT = 1 kHz,
1st 19 harmonics removed for SNR calculation
BW = 20 kHz, V_DD = 5 V, f_OUT = 1 kHz,
1st 19 harmonics removed for SNR calculation
BW = 20 kHz, V_DD = 5 V, f_OUT = 1 kHz,
1st 19 harmonics removed for SNR calculation
BW = 20 kHz, V_DD = 5 V, f_OUT = 1 kHz,
1st 19 harmonics removed for SNR calculation
V_REF = V_DD = 5 V
V_REF = V_DD = 3.6 V
V_DD = 5 V
V_DD = 3 V
V_DD = 5 V
V_DD = 3 V
MIN TYP
16
±3
±3
±0.25
±2
±0.05%
±0.02%
±5
±1
0.75
0
8
12
1.8
470
1000
0.1
0.1
1
50
20
2.5
5
95
–85
87
84
0
40
30
125
±1
0.7 × V_DD
0.9 × V_DD
MAX UNIT
Bits
±12
LSB
±8
±1 LSB
±12 mV
±0.5% mV
±0.2% mV
μV/°C
ppm of
FSR/°C
mV/V
V_REF
V
10
μs
V/μs
pF
nV-s
nV-s
Ω
mA
μs
dB
dB
dB
dB
V_DD
V
75
μA
45
kΩ
μA
0.3 × V_DD
V
0.1 × V_DD
V
3 pF
(1) Linearity calculated using a reduced code range of –32283 to 32063; output unloaded.
(2) Specified by design and characterization, not production tested.
Copyright © 2006–2016, Texas Instruments Incorporated
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