DAC8550_16 Datasheet, PDF (17/31 Pages) Texas Instruments – 16-bit, Ultra-Low Glitch, Voltage Output Digital-To-Analog Converter

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DAC8550
SLAS476F – MARCH 2006 – REVISED MARCH 2016
7.4 Device Functional Modes
7.4.1 Power-Down Modes
The DAC8550 supports four separate modes of operation. These modes are programmable by setting two bits
(PD1 and PD0) in the control register. Table 1 shows how the state of the bits corresponds to the mode of
operation of the device.
PD1 (DB17)
0
—
0
1
1
PD0 (DB16)
0
—
1
0
1
Table 1. Operating Modes
OPERATING MODE
Normal operation
Power-down modes
Output typically 1 kΩ to GND
Output typically 100 kΩ to GND
High-Z
When both bits are set to 0, the device works normally with a typical current consumption of 200 μA at 5 V.
However, for the three power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not only
does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a
resistor network of known values. The advantage with this configuration is that the output impedance of the
device is known while in power-down mode. There are three different options. The output is connected internally
to GND through a 1-kΩ resistor, a 100-kΩ resistor, or it is left open-circuited (High-Z). The output stage is
illustrated in Figure 48.
V_FB
Resistor
String
DAC
Amplifier
V_OUT
Power-Down
Circuitry
Resistor
Network
Figure 48. Output Stage During Power-Down
All analog circuitry is shut down when the power-down mode is activated. However, the contents of the DAC
register are unaffected when in power-down. The time to exit power-down is typically 2.5 μs for V_DD = 5 V, and 5
μs for V_DD = 3 V. See the Typical Characteristics for more information.
7.5 Programming
7.5.1 Serial Interface
The DAC8550 has a 3-wire serial interface (SYNC, SCLK, and D_IN), which is compatible with SPI, QSPI, and
Microwire interface standards, as well as most DSP interfaces. See Figure 1 for an example of a typical write
sequence.
The write sequence begins by bringing the SYNC line LOW. Data from the D_IN line are clocked into the 24-bit
shift register on each falling edge of SCLK. The serial clock frequency can be as high as 30 MHz, making the
DAC8550 compatible with high-speed DSPs. On the 24th falling edge of the serial clock, the last data bit is
clocked in and the programmed function is excuted (that is, a change in DAC register contents and/or a change
in the mode of operation).
At this point, the SYNC line may be kept LOW or brought HIGH. In either case, it must be brought HIGH for a
minimum of 33 ns before the next write sequence so that a falling edge of SYNC can initiate the next write
sequence. Since the SYNC buffer draws more current when the SYNC signal is HIGH than it does when it is
LOW, SYNC should be idled LOW between write sequences for lowest power operation of the part. As
mentioned above, it must be brought HIGH again just before the next write sequence.
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