DAC8550_16 Datasheet, PDF (18/31 Pages) Texas Instruments – 16-bit, Ultra-Low Glitch, Voltage Output Digital-To-Analog Converter

DAC8550
SLAS476F – MARCH 2006 – REVISED MARCH 2016
www.ti.com
Programming (continued)
7.5.2 Input Shift Register
The input shift register is 24 bits wide, as shown in Figure 49. The first six bits are unused bits. The next two bits
(PD1 and PD0) are control bits that control which mode of operation the part is in (normal mode or any one of
three power-down modes). For a more complete description of the various modes see Power-Down Modes. The
next 16 bits are the data bits. These bits are transferred to the DAC register on the 24th falling edge of SCLK.
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Unused
PD1 PD0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 49. DAC8550 Data Input Register Format
7.5.3 SYNC Interrupt
In a normal write sequence, the SYNC line is kept LOW for at least 24 falling edges of SCLK and the DAC is
updated on the 24th falling edge. However, if SYNC is brought HIGH before the 24th falling edge, it acts as an
interrupt to the write sequence. The shift register is reset and the write sequence is seen as invalid. Neither an
update of the DAC register contents nor a change in the operating mode occurs, as shown in Figure 50.
24th Falling Edge
CLK
24th Falling Edge
SYNC
D_IN
DB23
DB80
DB23
DB80
Valid Write Sequence: Output Updates
on the 24th Falling Edge
Figure 50. SYNC Interrupt Facility
18
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