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MSP430F4796IPZ Datasheet, PDF (53/89 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER
MSP430F47x
MIXED SIGNAL MICROCONTROLLER
SLAS629A -- MARCH 2009 -- REVISED APRIL 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (UART mode)
fUSCI
PARAMETER
USCI input clock frequency
TEST CONDITIONS
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
VCC
MIN TYP MAX UNIT
fSYSTEM MHz
fmax, BITCLK
Maximum BITCLK clock frequency
(equals baudrate in MBaud)
(see Note 1)
2.2 V /3 V
2
MHz
UART receive deglitch time
tτ
(see Note 2)
2.2 V
50 150
ns
3V
50 100
ns
NOTES: 1. The DCO wake-up time must be considered in LPM3/4 for baud rates above 1 MHz.
2. Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed.
USCI (SPI master mode) (see Figure 27 and Figure 28)
fUSCI
PARAMETER
USCI input clock frequency
TEST CONDITIONS
SMCLK, ACLK
Duty cycle = 50% ± 10%
VCC
MIN MAX UNIT
fSYSTEM MHz
tSU, MI
SOMI input data setup time
2.2 V
110
ns
3V
75
ns
tHD, MI
SOMI input data hold time
2.2 V
0
ns
3V
0
ns
tVALID, MO
SIMO output data valid time
UCLK edge to SIMO valid,
CL = 20 pF
2.2 V
3V
30 ns
20 ns
NOTE:
fUCxCLK
=
1
2tLO∕HI
with
tLO∕HI
≥
max(tVALID,MO(USCI)
+
t SU,SI(Slave),
tSU,MI(USCI)
+
t ) VALID,SO(Slave) .
For the slave’s parameters tSU, SI(Slave) and tVALID, SO(Slave) refer to the SPI parameters of the attached slave.
USCI (SPI slave mode) (see Figure 29 and Figure 30)
tSTE, LEAD
PARAMETER
STE lead time
STE low to clock
TEST CONDITIONS
VCC
2.2 V/3 V
MIN TYP MAX UNIT
50
ns
tSTE, LAG
STE lag time
Last clock to STE high
2.2 V/3 V
10
ns
tSTE, ACC
STE access time
STE low to SOMI data out
2.2 V/3 V
50
ns
tSTE, DIS
STE disable time
STE high to SOMI high impedance
2.2 V/3 V
50
ns
tSU, SI
SIMO input data setup time
2.2 V
20
ns
3V
15
ns
tHD, SI
SIMO input data hold time
2.2 V
10
ns
3V
10
ns
tVALID, SO
SOMI output data valid time
UCLK edge to SOMI valid,
CL = 20 pF
2.2 V
3V
75 110 ns
50 75 ns
NOTE:
fUCxCLK
=
1
2tLO∕HI
with
tLO∕HI
≥
max(tVALID,MO(Master)
+
tSU,SI(USCI),
tSU,MI(Master)
+
t ) VALID,SO(USCI) .
For the master’s parameters tSU, MI(Master) and tVALID, MO(Master) refer to the SPI parameters of the attached master.
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