THS4551 Datasheet, PDF (52/70 Pages) Texas Instruments – Low-Noise, Precision, 150-MHz, Fully Differential Amplifier

THS4551
SBOS778A – APRIL 2016 – REVISED AUGUST 2016
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10.2.3 ADC3k Driver with a 2nd-Order RLC Interstage Filter Application
The THS4551 is well suited to low-power, dc-coupled requirements driving low-power pipeline ADCs (such as
the ADC3241 25-MSPS, 14-bit, dual device). Figure 93 shows an example design taking a bipolar input to a
–1-dBFS swing at the ADC input of 1.8 V_PP. In this case, a 50-Ω source and input matching is assumed with a
gain of 5 V/V to the output pins with a 2nd-order interstage filter adding a –1-dB insertion loss. Full-scale voltage
at the input of R_T and R_G1 is then ±0.2 V. The 0.95-V output common-mode voltage is provided by the ADC. The
output filter provides a noise-power bandwidth limit with a low overshoot step response with no common-mode
level shift from the 0.95-V voltage provided by the ADC.
VS+
+
3.3 V
±
VS-
0V ⁺
±
ADC Output
Common-Mode
VOCM
Voltage
+
950 mV
±
50- Source
Impedance
50- Input Match,
Gain of 5 V/V from RT,
Single-Ended Source to
Differential Output
THS4551 Wideband,
Fully Differential Amplifier
RF1
1k
RS1
50
RG1
187
VS+
40.2
±
VIN
RT1
59
VOCM
+
FDA
±
+
PD
RG2
215
VS- ^VS+
40.2
10-MHz,
Second-Order
Bessel Filter
390 nH
360 pF
5.6
732
VOUT
ADC3241
Inputs
390 nH
5.6
RF2
1k
Copyright © 2016, Texas Instruments Incorporated
Figure 93. ADC3k Driver with a 2nd-Order RLC Interstage Filter
10.2.3.1 Design Requirements
For this design example, the requirements include:
• Provide a wideband, 50-Ω input impedance match for a single-ended source centered on ground.
• From the input termination, provide a gain of 5 V/V to the FDA output pins as a differential signal.
• Set the output common-mode operating point using the ADC common-mode output voltage as the VOCM
input to the THS4551 FDA.
• Implement a low-overshoot, noise-band-limiting filter between the FDA and the ADC. Use only differential
shunt elements in the filter to pass the FDA output common-mode voltage to the ADC with no level shifting.
• Design the filter as a –1-dB insertion loss filter with a low series resistor to limit the common-mode level shift
resulting from the ADC input sample-rate-dependent common-mode current.
10.2.3.2 Detailed Design Procedure
The design proceeds as follows:
• Select the feedback resistor to be 1 kΩ and use the values from Table 1 at a gain of 5 V/V to implement a
50-Ω input match with a gain of 5 V/V.
• Use a 3.3-V power supply and apply the ADC output common-mode voltage to the VOCM input pin of the
THS4551.
• Design a –1-dB insertion loss, 2nd-order RLC filter using the approach described in the RLC Filter Design for
ADC Interface Applications application note (SBAA108).
• Adjust the total resistive load target in the filter design to hit the standard value for the filter inductors.
• Convert the filter design to differential with only differential shunt elements. These elements must not be split
and connected to a center-point ground. This technique passes the output common-mode voltage from the
FDA to the ADC with no level shift error.
• Add a small series resistor at the ADC inputs. This resistor is not part of the filter design but spreads out the
sampling glitch energy to provide improved SFDR.
• Check the common-mode level shift from the FDA outputs to the ADC resulting from the clock-rate-dependent
common-mode current. This common-mode current into the ADC shifts the common-mode voltage slightly,
but can easily stay in range with a low series resistor in the filter design.
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