THS4551 Datasheet, PDF (43/70 Pages) Texas Instruments – Low-Noise, Precision, 150-MHz, Fully Differential Amplifier

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THS4551
SBOS778A – APRIL 2016 – REVISED AUGUST 2016
10.1.5 Operating the Power Shutdown Feature
The CMOS input pin must be asserted to the desired voltage for operation. An internal pullup resistor is not
provided on the PD pin so that off-state quiescent current can be minimized. For applications simply requiring the
device to be powered on when the supplies are present, tie the PD pin to the positive supply voltage.
The disable operation is referenced from the negative supply, normally ground. For split-supply operation, with
the negative supply below ground, a disable control voltage below ground is required to turn the THS4551 off. To
assure an off state condition, the disable control pin must be below a voltage within 0.55 V of the negative
supply.
For single-supply operation, a minimum of 1.7 V above the negative supply (ground in this case) is required to
assure on operation. This logic threshold range allows direct operation from a 1.8-V supply logic when the
THS4551 operates with a single positive supply and ground.
10.1.6 Designing Attenuators
Operating the THS4551 at a low dc noise gain (or with higher feedback resistors) can cause a lower phase
margin to exist, thus giving the response peaking illustrated in Figure 1 for the gain of a 0.1 (a 1/10 attenuator)
condition. Although operating the THS4551 as an attenuator is often useful, taking a large input range to a
controlled output common-mode voltage with a purely differential signal around the V_OCM voltage, the response
peaking illustrated in Figure 1 is usually undesirable. Several approaches can be used to reduce or eliminate this
peaking, usually at the cost of higher output noise. DC attenuation at the input usually increases the output noise
broadband, whereas using an ac noise gain shaping technique that peaks the noise only at higher frequencies is
more desirable. This peaking output noise can then be filtered off with the typical passive RC filters often used
after this stage. Figure 80 shows a simplified schematic for the gain of 0.1-V/V test from Figure 1.
Gain of 0.1 V/V,
DC-Coupled,
Single-Ended Source to
Differential Output
THS4551 Wideband,
Fully Differential Amplifier
RF1
1k
VS+
VS-
2.5 V ⁺
-2.5 V ⁺
VIN
±
±
RG1
10 k
VOCM
VS+
±
+
FDA
±
+
PD
VS- ^VS+
VOUT
RL
1k
RG2
10 k
RF2
1k
Copyright © 2016, Texas Instruments Incorporated
Figure 80. Divide-by-10 Attenuator Application for the THS4551
A 5-dB peaked response (see Figure 82) results from the configuration of Figure 80, which results from a
nominal 32° phase margin. This peaking can be eliminated by placing two feedback capacitors across the R_F
elements and a differential input capacitor. Adding these capacitors provides a transition from a resistively set
noise gain (NG1 = 1.1 in Figure 80) to a capacitive divider at high frequency, and flattening out to a higher noise
gain (NG2). The key for this approach is to target a Z_O where the noise gain begins to peak up. Using only the
following terms, and targeting a closed-loop flat (Butterworth) response, gives this solution sequence (from
Equation 11 to Equation 13) for Z_O and then the capacitor values. See the OPA847 data sheet (page 12) for a
discussion of this inverting noise gain shaping technique.
• Gain bandwidth product in Hz (135 MHz for the THS4551)
• Low-frequency noise gain, NG1 (equal to 1.1 in the attenuator gain of a 0.1-V/V design)
• The target high-frequency noise gain is selected to be higher than NG1 (NG2 = 5 V/V) in this example
• Feedback resistor value, R_F (is assumed balanced for this differential design = 1 kΩ)
From these elements, for any voltage feedback op amp or FDA, solve for Z_O as shown in Equation 11:
Z_O
GBP
NG1²
§
¨¨©¹
NG1
NG2
1
2
NG1
NG2
·
¸¸¹
(11)
Copyright © 2016, Texas Instruments Incorporated
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