THS4551 Datasheet, PDF (33/70 Pages) Texas Instruments – Low-Noise, Precision, 150-MHz, Fully Differential Amplifier

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THS4551
SBOS778A – APRIL 2016 – REVISED AUGUST 2016
The output pin voltage swing is 0.95 V ± 0.5 V or 0.45 V to 1.45 V. This swing is divided back to the input V_ICM
by a 215 / (215 + 1000) = 0.177 ratio. This ratio computes the input pin range as 79 mV to 0.256 V, matching the
input source swing results in Equation 7. The TINA-TI™ model also provides these input swings as shown in the
simplified circuit of Figure 73. The large centered swing is the differential output voltage at the THS4551 output
pins (which is actually the two outputs swinging ±0.5 V around a 0.95 V_CM), the small centered bipolar swing is
the input swing for the thevenized source of Figure 73, and the smallest V_PP swing on a dc offset is the input
V_ICM voltage at the non-signal side input for the circuit of Figure 73.
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
0
VIN+
V_OUT
V_S
100 200 300 400 500 600 700 800 900 1000
Time (ns)
D069
Figure 73. I/O Swing Simulation Using the TINA-TI™ Model
9.3.4 Output DC Error and Drift Calculations and the Effect of Resistor Imbalances
The THS4551 offers a trimmed input offset voltage and extremely low offset drift over the full –40°C to +125°C
operating range. This offset voltage combines with several other error contribution terms to produce an initial
25°C output offset error band and then a drift over temperature. For each error term, a gain must be assigned to
that term. For this analysis, only dc-coupled signal paths are considered. One new source of output error (versus
the typical op amp analysis) arises from the effect mismatched resistor values and ratios can have on the two
sides of the FDA. Any common-mode error or drift creates a differential output error through the slight
mismatches arising from the external feedback and gain setting resistor tolerances or standard value constraints.
The error terms (25°C and drift), along with the gain to the output differential voltage, include input offset voltage
and input offset current. Input offset voltage has a gain equal to the noise gain or 1 + R_F / R_G, where R_G is the
total dc impedance from the input pins back to the source or a dc reference (typically ground). Input offset current
has a gain to the differential output through the average feedback resistor value.
The remaining terms arise from an assumed range on both the absolute feedback resistor mismatch and the
mismatch in the divider ratio on each side of the FDA. The first of these resistor mismatch terms is the input bias
current that creates a differential output offset via R_F mismatch. For simplicity, the upper R_F and R_G values are
termed R_F1 and R_G1 with a ratio of R_F1 / R_G1 ≡ G1. The lower elements are defined as R_F2 and R_G2 with a ratio of
R_F2 / R_G2 ≡ G2. To compute worst-case contributions, a maximum variation in the design resistor tolerance is
used in the absolute and ratio mismatches.
For instance, ±1% tolerance resistors are assumed, giving a worst-case G1 that is 2% higher than nominal and a
G2 that is 2% lower than nominal with a worst-case R_F value mismatch of 2% as well. Using a 0.1% precision
resistor reduces the gain for the input bias current, but because these precision resistors are usually only
available in 1% value steps, a gain mismatch term may still need to be considered. For matched impedance
designs with R_T and R_G1 on a single-ended to differential stage, the standard value constraint imposes a fixed
mismatch in the initial feedback ratios with the tolerance of the resistors around the ratio if the non-signal input
side uses a single resistor for R_G2.
Define the selected external resistor tolerance as ±T (so for 1% tolerance resistors, T = 0.01). Input bias current
times the feedback resistor mismatch gain is ±2 × T × R_Fnom.
Anything that generates an output common-mode level or shift over temperature also generates an output
differential error term if the two feedback ratios, G1 and G2, are not equal. An error trying to produce a shift in
the output common-mode voltage is overridden by the common-mode control loop where the error becomes a
balanced differential error around the output V_OCM.
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